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Chip-level thermal analysis, modeling, and optimization using multilayer Green's function.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Chip-level thermal analysis, modeling, and optimization using multilayer Green's function./
Author:	Wang, Baohua.
Description:	1 online resource (149 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 4250.
Contained By:	Dissertation Abstracts International70-01B.
Subject:	Computer science. -
Online resource:	click for full text (PQDT)
ISBN:	9780549994398

Chip-level thermal analysis, modeling, and optimization using multilayer Green's function.
Wang, Baohua.

Chip-level thermal analysis, modeling, and optimization using multilayer Green's function. - 1 online resource (149 pages)

Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 4250.

Thesis (Ph.D.)--University of Michigan, 2008.

Includes bibliographical references

With the continual scaling of devices and interconnects, accurate analysis and effective optimization of the temperature distribution of a ULSI chip are increasingly important in predicting and ensuring the performance and reliability of the chip before fabrication. Motivated by the design challenges, this dissertation aims at a detailed study of the areas of thermal analysis, modeling, and optimization of ULSI chips. In particular, this dissertation introduces LOTAGre, a high-efficiency O (n lg n) multilayer Green's function-based thermal analysis method. LOTAGre can analyze ULSI chips consisting of multilayer heterogeneous heat conduction materials, with either wire-bonding packaging or flip-chip packaging, under uniform or nonuniform ambient temperatures. By integrating the eigen-expansion technique and the transmission line theory, this dissertation derives the multilayer heat conduction Green's function, including the s-domain version which can be used to compute the thermal transfer impedance between two arbitrary locations in the chip and establish compact thermal models for the critical components in the chip.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780549994398Subjects--Topical Terms:

573171
Computer science.
Index Terms--Genre/Form:

554714
Electronic books.

Chip-level thermal analysis, modeling, and optimization using multilayer Green's function.
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245 1 0 $a Chip-level thermal analysis, modeling, and optimization using multilayer Green's function.
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500 $a Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 4250.
500 $a Adviser: Pinaki Mazumder.
502 $a Thesis (Ph.D.)--University of Michigan, 2008.
504 $a Includes bibliographical references
520 $a With the continual scaling of devices and interconnects, accurate analysis and effective optimization of the temperature distribution of a ULSI chip are increasingly important in predicting and ensuring the performance and reliability of the chip before fabrication. Motivated by the design challenges, this dissertation aims at a detailed study of the areas of thermal analysis, modeling, and optimization of ULSI chips. In particular, this dissertation introduces LOTAGre, a high-efficiency O (n lg n) multilayer Green's function-based thermal analysis method. LOTAGre can analyze ULSI chips consisting of multilayer heterogeneous heat conduction materials, with either wire-bonding packaging or flip-chip packaging, under uniform or nonuniform ambient temperatures. By integrating the eigen-expansion technique and the transmission line theory, this dissertation derives the multilayer heat conduction Green's function, including the s-domain version which can be used to compute the thermal transfer impedance between two arbitrary locations in the chip and establish compact thermal models for the critical components in the chip.
520 $a To aid interconnect thermal analysis, this dissertation introduces a new Schafft-type interconnect temperature distribution model which is very flexible in addressing the effects of chip packaging, surrounding ambient temperatures, and the temperature gradients within the interconnect. An efficient O (n) method is introduced to solve the interconnect temperature distribution from the model.
520 $a To optimize the chip temperature distribution, this dissertation introduces an optimal power budget model that determines the optimal allocation of cell powers to different regions of the chip so that the resultant temperature distribution most closely approximates the target temperature distribution for the chip. The generalized minimal residue method and the conjugate gradient method are employed to construct top-level and front-level thermal optimizers to solve the optimal power budget efficiently. Finally, the dissertation describes the procedure to incorporate the optimal power budget model into the widely distributed Capo placement tool to enable thermal optimization in the cell placement stage.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Computer science. $3 573171
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0984
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Michigan. $3 845400
773 0 $t Dissertation Abstracts International $g 70-01B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3343244 $z click for full text (PQDT)