國立虎尾科技大學 |

Improving Energy Efficiency for CGRA Architectures.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Improving Energy Efficiency for CGRA Architectures./
作者:	Nayak, Ankita.
面頁冊數:	1 online resource (118 pages)
附註:	Source: Dissertations Abstracts International, Volume: 84-12, Section: B.
Contained By:	Dissertations Abstracts International84-12B.
標題:	Energy efficiency. -
電子資源:	click for full text (PQDT)
ISBN:	9798379652173

Improving Energy Efficiency for CGRA Architectures.
Nayak, Ankita.

Improving Energy Efficiency for CGRA Architectures. - 1 online resource (118 pages)

Source: Dissertations Abstracts International, Volume: 84-12, Section: B.

Thesis (Ph.D.)--Stanford University, 2023.

Includes bibliographical references

The rise of edge computing has resulted in a growing need for executing computationally intensive tasks within strict energy constraints. ASICs are typically used to achieve high performance and energy efficiency, but at the expense of hardware flexibility. Given the fast-paced evolution of edge applications, there is a pressing requirement for flexible yet energy-efficient architectures that can keep up with the latest trends.Traditionally, reconfigurable computing devices have used processors, where instructions configure the processor in each clock cycle to perform the desired operation. More recently, researchers have explored using Field Programmable Gate Arrays (FPGA), and Coarse-Grained Reconfigurable Architectures (CGRA), which configure the hardware in space (and not time) to provide programmable computing devices. In the space of spatial programmable architectures, CGRAs are a promising alternative to FPGAs due to their higher energy efficiency that comes from operating at a word-level granularity in logic and routing.This thesis introduces two methods to improve the energy efficiency of CGRAs. First, low-accesscost distributed memories are introduced into the processing elements. While similar to conventional register files, these memories are optimized to work with applications with streaming data, so they "push" the data to the computing elements. These memories help improve the energy efficiency of Deep Neural Network (DNN) applications on the CGRAs. The second method aims to improve the energy efficiency of CGRAs by introducing low-overhead fine-grained power domains to better optimize both active and idle power. Both these techniques have been integrated into a taped out SoC with a CGRA optimized for Deep Learning and Computer Vision applications.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798379652173Subjects--Topical Terms:

1175986
Energy efficiency.
Index Terms--Genre/Form:

554714
Electronic books.

Improving Energy Efficiency for CGRA Architectures.
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502 $a Thesis (Ph.D.)--Stanford University, 2023.
504 $a Includes bibliographical references
520 $a The rise of edge computing has resulted in a growing need for executing computationally intensive tasks within strict energy constraints. ASICs are typically used to achieve high performance and energy efficiency, but at the expense of hardware flexibility. Given the fast-paced evolution of edge applications, there is a pressing requirement for flexible yet energy-efficient architectures that can keep up with the latest trends.Traditionally, reconfigurable computing devices have used processors, where instructions configure the processor in each clock cycle to perform the desired operation. More recently, researchers have explored using Field Programmable Gate Arrays (FPGA), and Coarse-Grained Reconfigurable Architectures (CGRA), which configure the hardware in space (and not time) to provide programmable computing devices. In the space of spatial programmable architectures, CGRAs are a promising alternative to FPGAs due to their higher energy efficiency that comes from operating at a word-level granularity in logic and routing.This thesis introduces two methods to improve the energy efficiency of CGRAs. First, low-accesscost distributed memories are introduced into the processing elements. While similar to conventional register files, these memories are optimized to work with applications with streaming data, so they "push" the data to the computing elements. These memories help improve the energy efficiency of Deep Neural Network (DNN) applications on the CGRAs. The second method aims to improve the energy efficiency of CGRAs by introducing low-overhead fine-grained power domains to better optimize both active and idle power. Both these techniques have been integrated into a taped out SoC with a CGRA optimized for Deep Learning and Computer Vision applications.
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650 4 $a Neural networks. $3 1011215
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