國立虎尾科技大學 |

Formal Verification of Floating-Point Hardware Design = A Mathematical Approach /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Formal Verification of Floating-Point Hardware Design/ by David M. Russinoff.
Reminder of title:	A Mathematical Approach /
Author:	Russinoff, David M.
Description:	XXVIII, 436 p. 40 illus.online resource. :
Contained By:	Springer Nature eBook
Subject:	Computer arithmetic and logic units. -
Online resource:	https://doi.org/10.1007/978-3-030-87181-9
ISBN:	9783030871819

Formal Verification of Floating-Point Hardware Design = A Mathematical Approach /
Russinoff, David M.

Formal Verification of Floating-Point Hardware DesignA Mathematical Approach /[electronic resource] :by David M. Russinoff. - 2nd ed. 2022. - XXVIII, 436 p. 40 illus.online resource.

Part I - Register-Transfer Logic -- Basic Arithmetic Functions -- Bit Vectors -- Logical Operations -- Part II - Floating-Point Arithmetic -- Floating-Point Numbers -- Floating-Point Formats -- Rounding -- IEEE-Compliant Square Root -- Part III - Implementation of Elementary Operations -- Addition -- Multiplication -- SRT Division and Square Root -- FMA-Based Division -- Part IV - Comparative Architectures: SSE, x87, and Arm -- SSE Floating-Point Instructions -- x87 Instructions -- Arm Floating-Point -- Instructions -- Part V - Formal Verification of RTL Designs -- The RAC Modeling Language -- Double-Precision Multiplication and Scaling -- Double-Precision Addition and FMA -- Multi-Precision Radix-8 SRT Division -- 64-bit Integer Division -- Multi-Precision Radix-4 SRT Square Root -- Multi-Precision Radix-2 SRT Division -- Fused Multiply-Add of a Graphics Processor.

This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I—III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V.

ISBN: 9783030871819

Standard No.: 10.1007/978-3-030-87181-9doiSubjects--Topical Terms:

1030803
Computer arithmetic and logic units.

LC Class. No.: QA76.9.C62

Dewey Class. No.: 004.01513

Formal Verification of Floating-Point Hardware Design = A Mathematical Approach /
LDR:03926nam a22003975i 4500 001 1089268
003 DE-He213
005 20220303140533.0
007 cr nn 008mamaa
008 221228s2022 sz | s |||| 0|eng d
020 $a 9783030871819 $9 978-3-030-87181-9
024 7 $a 10.1007/978-3-030-87181-9 $2 doi
035 $a 978-3-030-87181-9
050 4 $a QA76.9.C62
072 7 $a UK $2 bicssc
072 7 $a COM036000 $2 bisacsh
072 7 $a UK $2 thema
082 0 4 $a 004.01513 $2 23
100 1 $a Russinoff, David M. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1309611
245 1 0 $a Formal Verification of Floating-Point Hardware Design $h [electronic resource] : $b A Mathematical Approach / $c by David M. Russinoff.
250 $a 2nd ed. 2022.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2022.
300 $a XXVIII, 436 p. 40 illus. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a Part I - Register-Transfer Logic -- Basic Arithmetic Functions -- Bit Vectors -- Logical Operations -- Part II - Floating-Point Arithmetic -- Floating-Point Numbers -- Floating-Point Formats -- Rounding -- IEEE-Compliant Square Root -- Part III - Implementation of Elementary Operations -- Addition -- Multiplication -- SRT Division and Square Root -- FMA-Based Division -- Part IV - Comparative Architectures: SSE, x87, and Arm -- SSE Floating-Point Instructions -- x87 Instructions -- Arm Floating-Point -- Instructions -- Part V - Formal Verification of RTL Designs -- The RAC Modeling Language -- Double-Precision Multiplication and Scaling -- Double-Precision Addition and FMA -- Multi-Precision Radix-8 SRT Division -- 64-bit Integer Division -- Multi-Precision Radix-4 SRT Square Root -- Multi-Precision Radix-2 SRT Division -- Fused Multiply-Add of a Graphics Processor.
520 $a This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings. This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I—III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V.
650 0 $a Computer arithmetic and logic units. $3 1030803
650 0 $a Computers. $3 565115
650 0 $a Microprocessors. $3 632481
650 0 $a Computer architecture. $3 528145
650 0 $a Electronic circuit design. $3 596419
650 1 4 $a Arithmetic and Logic Structures. $3 672631
650 2 4 $a Hardware Performance and Reliability. $3 1366872
650 2 4 $a Processor Architectures. $3 669787
650 2 4 $a Electronics Design and Verification. $3 1387809
650 2 4 $a Computer Hardware. $3 669779
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783030871802
776 0 8 $i Printed edition: $z 9783030871826
776 0 8 $i Printed edition: $z 9783030871833
856 4 0 $u https://doi.org/10.1007/978-3-030-87181-9
912 $a ZDB-2-SCS
912 $a ZDB-2-SXCS
950 $a Computer Science (SpringerNature-11645)
950 $a Computer Science (R0) (SpringerNature-43710)