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Soft Error Analysis and Design Space Exploration of Radiation-Hardened System-on-a-Chip Platforms.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Soft Error Analysis and Design Space Exploration of Radiation-Hardened System-on-a-Chip Platforms./
Author:	Atli, Oguz.
Description:	1 online resource (108 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 85-11, Section: B.
Contained By:	Dissertations Abstracts International85-11B.
Subject:	Computer engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9798382603261

Soft Error Analysis and Design Space Exploration of Radiation-Hardened System-on-a-Chip Platforms.
Atli, Oguz.

Soft Error Analysis and Design Space Exploration of Radiation-Hardened System-on-a-Chip Platforms. - 1 online resource (108 pages)

Source: Dissertations Abstracts International, Volume: 85-11, Section: B.

Thesis (Ph.D.)--Carnegie Mellon University, 2024.

Includes bibliographical references

System-on-chips (SoCs) with specialized accelerators have become prevalent as compute-intensive applications such as deep neural networks (DNNs) have become more widespread. Such SoCs with DNN accelerators are getting deployed more and more in security-critical fields like autonomous driving and space exploration, which makes the reliability of such platforms very important. Particle radiation present in Earth's atmosphere and space poses a reliability threat to safety-critical applications, as the free charge collected by the storage nodes of an integrated circuit (IC) can flip the stored bits and cause system-level failure. IC designers, especially ones working for the compute requirements of space missions, employ structured redundancy techniques such as error correcting codes (ECC) and double/triple modular redundancy (DM-R/TMR) to detect and correct the soft errors in their designs. However, such methods have high power, performance and area (PPA) overheads, and require long RTL design and verification cycles. Due to the manual RTL edits necessary to implement each hardening method and the long and slow fault injection (FI) experiments required to assess the reliability of the final system, designers often can't iterate on their design sufficiently many times to minimize the incurred PPA costs.In this work, we introduce RadTool, a toolset that aids designers with architecting complex radiation-hardened designs such as SoCs with multiple clock domains and accelerators. RadTool contains FIERA, an FPGA-accelerated soft error injection tool, and RIERA, an automated RTL redundancy insertion tool. FIERA makes use of FPGA-based emulation for error injection, so it is 4-5 orders of magnitude faster than RTL simulation-based approaches. FIERA instruments the FIRRTL representation of the input RTL and employs stop-clock fault injection, which makes the platform flexible and extensible, and enables 47% more efficient LUT mapping of the instrumentation logic compared to previous work. RIERA similarly operates on FIRRTL and can insert radiation hardening methods such as DMR, TMR, and scrubber-backed ECC to any design hierarchy with the desired level of granularity. The Bayesian optimization engine in RIERA can also search through different radiation-hardening methods and come up with Pareto-optimal designs in terms of their radiation-hardness and PPA overhead. The combination of both these tools allows designers to rapidly prototype different radiation-hardened designs and evaluate each of them with accelerated FI experiments, greatly tightening their design and verification loop.As a case study of FIERA, we evaluate soft error vulnerabilities of sample SoCs with DNN accelerators under DNN and benchmark workloads. Our experiments show that unprotected instruction storage and control logic dominate application failure rates and that data movement and storage patterns can cause up to 13x difference in program error rate. We explore the effectiveness of RIERA by using it to pick the design partitions to harden within a RISC-V SoC to optimally satisfy various PPA and time-to-failure specs. We use RIERA to generate designs that compared to a fully TMR and ECC-protected design, achieve 65% of the time-to-failure with 45% of the area overhead, and achieve 86% of the time-to-failure with 59% of the area overhead. We also describe two test chips that were taped out on Intel 22FFL and Intel 16 processes respectively to demonstrate the real-life implications of RadTool. The test chips contain representative SoCs with varying levels of redundancy added to their memories and registers. We have performed radiation tests on these test chips to verify the accuracy of RadTool, showing that we can rapidly predict the mean time-to-failures of sample matmul and sort applications to within 14.1% and 4.6% respectively using RadTool at the RTL design stage, without the need for expensive silicon prototypes.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798382603261Subjects--Topical Terms:

569006
Computer engineering.
Subjects--Index Terms:

AI acceleratorsIndex Terms--Genre/Form:

554714
Electronic books.

Soft Error Analysis and Design Space Exploration of Radiation-Hardened System-on-a-Chip Platforms.
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520 $a System-on-chips (SoCs) with specialized accelerators have become prevalent as compute-intensive applications such as deep neural networks (DNNs) have become more widespread. Such SoCs with DNN accelerators are getting deployed more and more in security-critical fields like autonomous driving and space exploration, which makes the reliability of such platforms very important. Particle radiation present in Earth's atmosphere and space poses a reliability threat to safety-critical applications, as the free charge collected by the storage nodes of an integrated circuit (IC) can flip the stored bits and cause system-level failure. IC designers, especially ones working for the compute requirements of space missions, employ structured redundancy techniques such as error correcting codes (ECC) and double/triple modular redundancy (DM-R/TMR) to detect and correct the soft errors in their designs. However, such methods have high power, performance and area (PPA) overheads, and require long RTL design and verification cycles. Due to the manual RTL edits necessary to implement each hardening method and the long and slow fault injection (FI) experiments required to assess the reliability of the final system, designers often can't iterate on their design sufficiently many times to minimize the incurred PPA costs.In this work, we introduce RadTool, a toolset that aids designers with architecting complex radiation-hardened designs such as SoCs with multiple clock domains and accelerators. RadTool contains FIERA, an FPGA-accelerated soft error injection tool, and RIERA, an automated RTL redundancy insertion tool. FIERA makes use of FPGA-based emulation for error injection, so it is 4-5 orders of magnitude faster than RTL simulation-based approaches. FIERA instruments the FIRRTL representation of the input RTL and employs stop-clock fault injection, which makes the platform flexible and extensible, and enables 47% more efficient LUT mapping of the instrumentation logic compared to previous work. RIERA similarly operates on FIRRTL and can insert radiation hardening methods such as DMR, TMR, and scrubber-backed ECC to any design hierarchy with the desired level of granularity. The Bayesian optimization engine in RIERA can also search through different radiation-hardening methods and come up with Pareto-optimal designs in terms of their radiation-hardness and PPA overhead. The combination of both these tools allows designers to rapidly prototype different radiation-hardened designs and evaluate each of them with accelerated FI experiments, greatly tightening their design and verification loop.As a case study of FIERA, we evaluate soft error vulnerabilities of sample SoCs with DNN accelerators under DNN and benchmark workloads. Our experiments show that unprotected instruction storage and control logic dominate application failure rates and that data movement and storage patterns can cause up to 13x difference in program error rate. We explore the effectiveness of RIERA by using it to pick the design partitions to harden within a RISC-V SoC to optimally satisfy various PPA and time-to-failure specs. We use RIERA to generate designs that compared to a fully TMR and ECC-protected design, achieve 65% of the time-to-failure with 45% of the area overhead, and achieve 86% of the time-to-failure with 59% of the area overhead. We also describe two test chips that were taped out on Intel 22FFL and Intel 16 processes respectively to demonstrate the real-life implications of RadTool. The test chips contain representative SoCs with varying levels of redundancy added to their memories and registers. We have performed radiation tests on these test chips to verify the accuracy of RadTool, showing that we can rapidly predict the mean time-to-failures of sample matmul and sort applications to within 14.1% and 4.6% respectively using RadTool at the RTL design stage, without the need for expensive silicon prototypes.
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