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Low-Power and High-Performance SRAM Design in High Variability Advanced CMOS Technology.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Low-Power and High-Performance SRAM Design in High Variability Advanced CMOS Technology./
Author:	Ataei, Fatemeh.
Description:	1 online resource (138 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.
Contained By:	Dissertation Abstracts International79-04B(E).
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9780355377279

Low-Power and High-Performance SRAM Design in High Variability Advanced CMOS Technology.
Ataei, Fatemeh.

Low-Power and High-Performance SRAM Design in High Variability Advanced CMOS Technology. - 1 online resource (138 pages)

Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.

Thesis (Ph.D.)

Includes bibliographical references

As process technologies shrink, the size and number of memories on a chip are exponentially increasing. Embedded SRAMs are a critical component in modern digital systems, and they strongly impact the overall power, performance, and area. To promote memory-related research in academia, this dissertation introduces OpenRAM, a flexible, portable and open-source memory compiler and characterization methodology for generating and verifying memory designs across different technologies.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780355377279Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Low-Power and High-Performance SRAM Design in High Variability Advanced CMOS Technology.
LDR:03344ntm a2200385Ki 4500 001 910736
005 20180517112609.5
006 m o u
007 cr mn||||a|a||
008 190606s2017 xx obm 000 0 eng d
020 $a 9780355377279
035 $a (MiAaPQ)AAI10268098
035 $a (MiAaPQ)okstate:15031
035 $a AAI10268098
040 $a MiAaPQ $b eng $c MiAaPQ
099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Ataei, Fatemeh. $3 1182178
245 1 0 $a Low-Power and High-Performance SRAM Design in High Variability Advanced CMOS Technology.
264 0 $c 2017
300 $a 1 online resource (138 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.
500 $a Adviser: James E. Stine.
502 $a Thesis (Ph.D.) $c Oklahoma State University $d 2017.
504 $a Includes bibliographical references
520 $a As process technologies shrink, the size and number of memories on a chip are exponentially increasing. Embedded SRAMs are a critical component in modern digital systems, and they strongly impact the overall power, performance, and area. To promote memory-related research in academia, this dissertation introduces OpenRAM, a flexible, portable and open-source memory compiler and characterization methodology for generating and verifying memory designs across different technologies.
520 $a In addition, SRAM designs, focusing on improving power consumption, access time and bitcell stability are explored in high variability advanced CMOS technologies. To have a stable read/write operation for SRAM in high variability process nodes, a differential-ended single-port 8T bitcell is proposed that improves the read noise margin, write noise margin and readout bitcell current by 45%, 48% and 21%, respectively, compared to a conventional 6T bitcell. Also, a differential-ended single-port 12T bitcell for subthreshold operation is proposed that solves the half-select disturbance and allows efficient bit-interleaving. 12T bitcell has a leakage control mechanism which helps to reduce the power consumption and provides operation down to 0.3 V. Both 8T and 12T bitcells are analyzed in a 64 kb SRAM array using 32 nm technology. Besides, to further improve the access time and power consumption, two tracking circuits (multi replica bitline delay and reconfigurable replica bitline delay techniques) are proposed to aid the generation of accurate and optimum sense amplifier set time.
520 $a An error tolerant SRAM architecture suitable for low voltage video application with dynamic power-quality management is also proposed in this dissertation. This memory uses three power supplies to improve the SRAM stability in low voltages. The proposed triple-supply approach achieves 63% improvement in image quality and 69% reduction in power consumption compared to a single-supply 64 kb SRAM array at 0.70 V.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
650 4 $a Computer engineering. $3 569006
650 4 $a Computer science. $3 573171
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
690 $a 0464
690 $a 0984
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Oklahoma State University. $b Electrical Engineering. $3 1182179
773 0 $t Dissertation Abstracts International $g 79-04B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10268098 $z click for full text (PQDT)