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Advanced HDL Synthesis and SOC Prototyping = RTL Design Using Verilog /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Advanced HDL Synthesis and SOC Prototyping / by Vaibbhav Taraate.
Reminder of title:	RTL Design Using Verilog /
Author:	Taraate, Vaibbhav.
Description:	XXI, 307 p. 263 illus., 196 illus. in color.online resource. :
Contained By:	Springer Nature eBook
Subject:	Electronic circuits. -
Online resource:	https://doi.org/10.1007/978-981-10-8776-9
ISBN:	9789811087769

Advanced HDL Synthesis and SOC Prototyping = RTL Design Using Verilog /
Taraate, Vaibbhav.

Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog /[electronic resource] :by Vaibbhav Taraate. - 1st ed. 2019. - XXI, 307 p. 263 illus., 196 illus. in color.online resource.

Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.

ISBN: 9789811087769

Standard No.: 10.1007/978-981-10-8776-9doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Advanced HDL Synthesis and SOC Prototyping = RTL Design Using Verilog /
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505 0 $a Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
520 $a This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
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