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VLSI-SoC: New Technology Enabler = 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	VLSI-SoC: New Technology Enabler/ edited by Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas, Ricardo Reis.
Reminder of title:	27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers /
other author:	Metzler, Carolina.
Description:	XVII, 345 p. 214 illus., 129 illus. in color.online resource. :
Contained By:	Springer Nature eBook
Subject:	Computer organization. -
Online resource:	https://doi.org/10.1007/978-3-030-53273-4
ISBN:	9783030532734

VLSI-SoC: New Technology Enabler = 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers /
VLSI-SoC: New Technology Enabler27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers /[electronic resource] :edited by Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas, Ricardo Reis. - 1st ed. 2020. - XVII, 345 p. 214 illus., 129 illus. in color.online resource. - IFIP Advances in Information and Communication Technology,5861868-4238 ;. - IFIP Advances in Information and Communication Technology,449.

Software-Based Self-Test for Delay Faults -- On Test Generation for Microprocessors for Extended Class of Functional Faults -- Robust FinFET Schmitt Trigger Designs for Low Power Applications -- An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults -- Process Variability Impact on the SET Response of FinFET Multi-level Design -- Efficient Soft Error Vulnerability Analysis Using Non-Intrusive Fault Injection Techniques -- A Statistical Wafer Scale Error and Redundancy Analysis Simulator -- Hardware-enabled Secure Firmware Updates in Embedded Systems -- Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance -- Security Aspects of Real-time MPSoCs: The Flaws and Opportunities of Preemptive NoCs -- Offset-Compensation Systems for Multi-Gbit/s Optical Receivers -- Accelerating Inference on Binary Neural Networks with Digital RRAM Processing -- Semi- and Fully-Random Access LUTs for Smooth Functions -- A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors -- Exploiting Heterogeneous Mobile Architectures through a Unified Runtime Framework.

This book contains extended and revised versions of the best papers presented at the 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, held in Cusco, Peru, in October 2019. The 15 full papers included in this volume were carefully reviewed and selected from the 28 papers (out of 82 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like heterogeneous, neuromorphic and brain-inspired, biologically-inspired, approximate computing systems.

ISBN: 9783030532734

Standard No.: 10.1007/978-3-030-53273-4doiSubjects--Topical Terms:

596298
Computer organization.

LC Class. No.: QA76.9.C643

Dewey Class. No.: 004.6

VLSI-SoC: New Technology Enabler = 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers /
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