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System reduction for nanoscale IC design

Record Type:	Language materials, printed : Monograph/item
Title/Author:	System reduction for nanoscale IC design/ edited by Peter Benner.
other author:	Benner, Peter.
Published:	Cham :Springer International Publishing : : 2017.,
Description:	xi, 197 p. :ill., digital ; : 24 cm.;
Contained By:	Springer eBooks
Subject:	Integrated circuits - Design and construction. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-07236-4
ISBN:	9783319072364

System reduction for nanoscale IC design
System reduction for nanoscale IC design[electronic resource] /edited by Peter Benner. - Cham :Springer International Publishing :2017. - xi, 197 p. :ill., digital ;24 cm. - Mathematics in industry,201612-3956 ;. - Mathematics in industry ;18. .

Preface -- 1 Model order reduction of integrated circuits in electrical networks: Michael Hinze, Martin Kunkel, Ulrich Matthes, and Morten Vierling -- 2 Element-based model reduction in circuit simulation: Andreas Steinbrecher and Tatjana Stykel -- 3 Reduced Representation of Power Grid Models: Peter Benner and Andre Schneider -- 4 Coupling of numeric/symbolic reduction methods for generating parametrized models of nanoelectronic systems: Oliver Schmidt, Matthias Hauser, and Patrick Lang -- 5 Low-Rank Cholesky Factor Krylov Subspace Methods for Generalized Projected Lyapunov Equations: Matthias Bollhofer and Andre K. Eppler -- Index.

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.

ISBN: 9783319072364

Standard No.: 10.1007/978-3-319-07236-4doiSubjects--Topical Terms:

561265
Integrated circuits
--Design and construction.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

System reduction for nanoscale IC design
LDR:02673nam a2200337 a 4500 001 905804
003 DE-He213
005 20180117113106.0
006 m d
007 cr nn 008maaau
008 190308s2017 gw s 0 eng d
020 $a 9783319072364 $q (electronic bk.)
020 $a 9783319072357 $q (paper)
024 7 $a 10.1007/978-3-319-07236-4 $2 doi
035 $a 978-3-319-07236-4
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874
072 7 $a PDE $2 bicssc
072 7 $a COM014000 $2 bisacsh
072 7 $a MAT003000 $2 bisacsh
082 0 4 $a 621.3815 $2 23
090 $a TK7874 $b .S995 2017
245 0 0 $a System reduction for nanoscale IC design $h [electronic resource] / $c edited by Peter Benner.
260 $a Cham : $c 2017. $b Springer International Publishing : $b Imprint: Springer,
300 $a xi, 197 p. : $b ill., digital ; $c 24 cm.
490 1 $a Mathematics in industry, $x 1612-3956 ; $v 20
505 0 $a Preface -- 1 Model order reduction of integrated circuits in electrical networks: Michael Hinze, Martin Kunkel, Ulrich Matthes, and Morten Vierling -- 2 Element-based model reduction in circuit simulation: Andreas Steinbrecher and Tatjana Stykel -- 3 Reduced Representation of Power Grid Models: Peter Benner and Andre Schneider -- 4 Coupling of numeric/symbolic reduction methods for generating parametrized models of nanoelectronic systems: Oliver Schmidt, Matthias Hauser, and Patrick Lang -- 5 Low-Rank Cholesky Factor Krylov Subspace Methods for Generalized Projected Lyapunov Equations: Matthias Bollhofer and Andre K. Eppler -- Index.
520 $a This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.
650 0 $a Integrated circuits $x Design and construction. $3 561265
650 0 $a Nanoelectronics $x Design and construction. $3 783552
650 1 4 $a Mathematics. $3 527692
650 2 4 $a Computational Science and Engineering. $3 670319
650 2 4 $a Mathematical Modeling and Industrial Mathematics. $3 669172
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
650 2 4 $a Computer-Aided Engineering (CAD, CAE) and Design. $3 669928
650 2 4 $a Algorithms. $3 527865
650 2 4 $a Appl.Mathematics/Computational Methods of Engineering. $3 669335
700 1 $a Benner, Peter. $3 672513
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer eBooks
830 0 $a Mathematics in industry ; $v 18. $3 886833
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-07236-4
950 $a Mathematics and Statistics (Springer-11649)