國立虎尾科技大學 |

Towards a Programmable Dataplane.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Towards a Programmable Dataplane./
Author:	Wang, Han.
Description:	1 online resource (287 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.
Contained By:	Dissertation Abstracts International78-11B(E).
Subject:	Computer science. -
Online resource:	click for full text (PQDT)
ISBN:	9781369885408

Towards a Programmable Dataplane.
Wang, Han.

Towards a Programmable Dataplane. - 1 online resource (287 pages)

Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.

Thesis (Ph.D.)

Includes bibliographical references

Programmable network dataplanes can significantly improve the flexibility and functionality of computer networks. This dissertation investigates two building blocks of network dataplane programming for network devices: the packet processing pipeline and network device interface. In the first part of the dissertation, we show that designing packet processing pipelines on hardware can be fast and flexible (programmable). A network dataplane compiler and runtime is presented that generates a custom FPGA dataplane designed and built from a dataplane programming language called P4 (programming protocol independent packet processors). P4FPGA generates designs that can be synthesized to either Xilinx or Altera FPGAs. We have benchmarked several representative P4 programs, and the experiments show that code generated by P4FPGA runs at line-rate at all packet sizes with latencies comparable to commercial ASICs. In the second part of the dissertation, we present a programmable network interface for the network dataplane. We show that a software programmable physical layer (programmable PHY) can capture and control the timing of physical layer bits with sub-nanosecond precision greatly increasing precision in network measurements. The benefits of a programmable PHY is demonstrated with an available bandwidth estimation algorithm and a decentralized clock synchronization protocol that provides bounded precision where no two clocks differ by more than tens of nanoseconds.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781369885408Subjects--Topical Terms:

573171
Computer science.
Index Terms--Genre/Form:

554714
Electronic books.

Towards a Programmable Dataplane.
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099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Wang, Han. $3 1179332
245 1 0 $a Towards a Programmable Dataplane.
264 0 $c 2017
300 $a 1 online resource (287 pages)
336 $a text $b txt $2 rdacontent
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500 $a Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.
500 $a Adviser: Hakim Weatherspoon.
502 $a Thesis (Ph.D.) $c Cornell University $d 2017.
504 $a Includes bibliographical references
520 $a Programmable network dataplanes can significantly improve the flexibility and functionality of computer networks. This dissertation investigates two building blocks of network dataplane programming for network devices: the packet processing pipeline and network device interface. In the first part of the dissertation, we show that designing packet processing pipelines on hardware can be fast and flexible (programmable). A network dataplane compiler and runtime is presented that generates a custom FPGA dataplane designed and built from a dataplane programming language called P4 (programming protocol independent packet processors). P4FPGA generates designs that can be synthesized to either Xilinx or Altera FPGAs. We have benchmarked several representative P4 programs, and the experiments show that code generated by P4FPGA runs at line-rate at all packet sizes with latencies comparable to commercial ASICs. In the second part of the dissertation, we present a programmable network interface for the network dataplane. We show that a software programmable physical layer (programmable PHY) can capture and control the timing of physical layer bits with sub-nanosecond precision greatly increasing precision in network measurements. The benefits of a programmable PHY is demonstrated with an available bandwidth estimation algorithm and a decentralized clock synchronization protocol that provides bounded precision where no two clocks differ by more than tens of nanoseconds.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Computer science. $3 573171
650 4 $a Computer engineering. $3 569006
650 4 $a Communication. $3 556422
655 7 $a Electronic books. $2 local $3 554714
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690 $a 0464
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710 2 $a Cornell University. $b Electrical & Computer Engrng. $3 1179333
773 0 $t Dissertation Abstracts International $g 78-11B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10255835 $z click for full text (PQDT)