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Timing performance of nanometer digital circuits under process variations

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Timing performance of nanometer digital circuits under process variations/ by Victor Champac, Jose Garcia Gervacio.
Author:	Champac, Victor.
other author:	Garcia Gervacio, Jose.
Published:	Cham :Springer International Publishing : : 2018.,
Description:	xviii, 185 p. :ill., digital ; : 24 cm.;
Contained By:	Springer eBooks
Subject:	Nanoelectronics - Materials. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-75465-9
ISBN:	9783319754659

Timing performance of nanometer digital circuits under process variations
Champac, Victor.

Timing performance of nanometer digital circuits under process variations[electronic resource] /by Victor Champac, Jose Garcia Gervacio. - Cham :Springer International Publishing :2018. - xviii, 185 p. :ill., digital ;24 cm. - Frontiers in electronic testing,v.390929-1296 ;. - Frontiers in electronic testing ;v.39..

Introduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues.

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level "design hints" are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.

ISBN: 9783319754659

Standard No.: 10.1007/978-3-319-75465-9doiSubjects--Topical Terms:

745158
Nanoelectronics
--Materials.

LC Class. No.: TK7874.84 / .C436 2018

Dewey Class. No.: 621.3815

Timing performance of nanometer digital circuits under process variations
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245 1 0 $a Timing performance of nanometer digital circuits under process variations $h [electronic resource] / $c by Victor Champac, Jose Garcia Gervacio.
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505 0 $a Introduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues.
520 $a This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level "design hints" are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.
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