Language:
English
繁體中文
Help
Login
Back
Switch To:
Labeled
|
MARC Mode
|
ISBD
RTL hardware design using VHDL = coding for efficiency, portability, and scalability /
Record Type:
Language materials, printed : Monograph/item
Title/Author:
RTL hardware design using VHDL/ Pong P. Chu.
Reminder of title:
coding for efficiency, portability, and scalability /
Author:
Chu, Pong P.,
Published:
Hoboken, N.J. :Wiley-Interscience, : c2006.,
Description:
1 online resource (xxiii, 669 p.) :ill. :
Subject:
Digital electronics - Data processing. -
Online resource:
http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5237648
ISBN:
0471720925 (alk. paper)
RTL hardware design using VHDL = coding for efficiency, portability, and scalability /
Chu, Pong P.,1959-
RTL hardware design using VHDL
coding for efficiency, portability, and scalability /[electronic resource] :Pong P. Chu. - Hoboken, N.J. :Wiley-Interscience,c2006. - 1 online resource (xxiii, 669 p.) :ill.
Includes bibliographical references (p. 665-666) and index.
Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice.
ISBN: 0471720925 (alk. paper)
Standard No.: 10.1002/0471786411doiSubjects--Topical Terms:
632776
Digital electronics
--Data processing.
LC Class. No.: TK7868.D5 / C46 2006
Dewey Class. No.: 621.39/2
RTL hardware design using VHDL = coding for efficiency, portability, and scalability /
LDR
:01790cam 2200325Ia 4500
001
670373
003
OCoLC
005
20121225141818.0
006
m o d
007
cr gn|
008
130624s2006 njua ob 001 0 eng d
020
$a
0471720925 (alk. paper)
020
$a
9780471720928 (alk. paper)
020
$a
0471786411 (electronic bk.)
020
$a
9780471786412 (electronic bk.)
024
7
$a
10.1002/0471786411
$2
doi
029
0
$a
DG1
$b
jws02620776
035
$a
(OCoLC)85820978
035
$a
ocm85820978
040
$a
DG1
$b
eng
$c
DG1
$d
OKU
$d
UMC
$d
IEEEE
$d
DG1
$d
OCLCQ
049
$a
HISA
050
4
$a
TK7868.D5
$b
C46 2006
082
0 4
$a
621.39/2
$2
22
100
1
$a
Chu, Pong P.,
$d
1959-
$3
596740
245
1 0
$a
RTL hardware design using VHDL
$h
[electronic resource] :
$b
coding for efficiency, portability, and scalability /
$c
Pong P. Chu.
260
$a
Hoboken, N.J. :
$b
Wiley-Interscience,
$c
c2006.
300
$a
1 online resource (xxiii, 669 p.) :
$b
ill.
504
$a
Includes bibliographical references (p. 665-666) and index.
505
0
$a
Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice.
650
0
$a
Digital electronics
$x
Data processing.
$3
632776
650
0
$a
VHDL (Computer hardware description language)
$3
591587
710
2
$a
John Wiley & Sons.
$3
771620
856
4 0
$3
IEEE Xplore
$u
http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5237648
938
$a
Wiley Subscription Services
$b
WILY
$n
jws02620776
994
$a
92
$b
TWHIS
based on 0 review(s)
Multimedia
Reviews
Add a review
and share your thoughts with other readers
Export
pickup library
Processing
...
Change password
Login
Please sign in
User name
Password
Remember me on this computer
Cancel
Forgot your password?