Cerny, Eduard.

Overview

Works:	1 works in 1 publications in 1 languages

Titles

SVA: The Power of Assertions in SystemVerilog by: Cerny, Eduard.; Havlicek, John.; Dudani, Surrendra.; SpringerLink (Online service); Korchemny, Dmitry. (Language materials, printed) , [http://id.loc.gov/vocabulary/relators/aut]

SVA = The Power of Assertions in SystemVerilog / by: Cerny, Eduard.; SpringerLink (Online service) (Language materials, printed)

Subjects

Electronic Circuits and Devices. Circuits and Systems. Microprocessors. Engineering. Electronic circuits. SystemVerilog (Computer hardware description language) Processor Architectures.