Cerny, Eduard.

概要

作品:	1 作品在 1 項出版品 1 種語言

書目資訊

SVA: The Power of Assertions in SystemVerilog by: Cerny, Eduard.; Havlicek, John.; Dudani, Surrendra.; SpringerLink (Online service); Korchemny, Dmitry. (書目-語言資料,印刷品) , [http://id.loc.gov/vocabulary/relators/aut]

SVA = The Power of Assertions in SystemVerilog / by: Cerny, Eduard.; SpringerLink (Online service) (書目-語言資料,印刷品)

主題

Electronic Circuits and Devices. Circuits and Systems. Microprocessors. Engineering. Electronic circuits. SystemVerilog (Computer hardware description language) Processor Architectures.