Kawecka, Elżbieta.
概要
| 作品: | 0 作品在 0 項出版品 0 種語言 | |
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書目資訊
Logic Synthesis for VLSI-Based Combined Finite State Machines = Synthesis Targeting ASICs, CPLDs and FPGAs /
by:
Mazurkiewicz, Małgorzata.; Barkalov, Alexander.; Kawecka, Elżbieta.; SpringerLink (Online service); Mielcarek, Kamil.; Titarenko, Larysa.
(書目-語言資料,印刷品)
, [http://id.loc.gov/vocabulary/relators/aut]