語系:
繁體中文
English
說明(常見問題)
登入
回首頁
切換:
標籤
|
MARC模式
|
ISBD
Long-Term Reliability of Nanometer V...
~
Kim, Taeyoung.
Long-Term Reliability of Nanometer VLSI Systems = Modeling, Analysis and Optimization /
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Long-Term Reliability of Nanometer VLSI Systems/ by Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr.
其他題名:
Modeling, Analysis and Optimization /
作者:
Tan, Sheldon.
其他作者:
Tahoori, Mehdi.
面頁冊數:
XLI, 460 p. 211 illus., 195 illus. in color.online resource. :
Contained By:
Springer Nature eBook
標題:
Electronic circuits. -
電子資源:
https://doi.org/10.1007/978-3-030-26172-6
ISBN:
9783030261726
Long-Term Reliability of Nanometer VLSI Systems = Modeling, Analysis and Optimization /
Tan, Sheldon.
Long-Term Reliability of Nanometer VLSI Systems
Modeling, Analysis and Optimization /[electronic resource] :by Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr. - 1st ed. 2019. - XLI, 460 p. 211 illus., 195 illus. in color.online resource.
Part I. New physics-based EM analysis and system-level dynamic reliability management -- Chapter 1. Introduction -- Chapter 2. Physics Based EM Modeling -- Chapter 3. Fast EM Stress Evolution Analysis Using Krylov Subspace Method -- Chapter 4. Fast EM Immortatlity Analysis For Multisegment Copper Interconnect Wires -- Chapter 5. Dynamic EM Models For Transient Stress Evolution and Recovery -- Chapter 6. Compact EM Models for Multi-SEgment Interconnect Wires -- Chapter 7. EM Assesment for Power Grid Networks -- Chapter 8. Resource Based EM Modeling for Multi-Crore Microprocessors -- Chapter 9. DRM and Optimization for Real Time Embedded Systems -- Chapter 10. Learning Based DRM and Energy Optimization for Many Core Dark Silicaon Processors -- Chapter 11. Recovery Aware DRM for Near Threshold Dark Silicon Processors -- Chapter 12. Cross-Layer DRM and Optimization For Datacenter Systems -- Part II. Transistor Aging Effects and Reliability -- 13. Introduction -- Chapter 14. Aging AWare Timings Analysis -- Chapter 15. Aging Aware Standard Cell Library Optimization Methods -- Chapter 16. Aging Effects In Sequential Elements -- Chapter 17. Aging Guardband Reduction Through Selective Flip Flop Optimization -- Chapter 18. Workload Aware Static Aging Monitoring and Mitigation of Timing Critical Flip Flops -- Chapter 19. Aging Relaxation at Micro Architecture Level Using Special NOPS -- Chapter 20. Extratime Modelling and Analyis of Transistor Agin at Microarchitecture Level -- Chapter 21. Reducing Processor Wearout By Exploiting The Timing Slack of Instructions.
This book provides readers with a detailed reference regarding two of the most important long-term reliability and aging effects on nanometer integrated systems, electromigrations (EM) for interconnect and biased temperature instability (BTI) for CMOS devices. The authors discuss in detail recent developments in the modeling, analysis and optimization of the reliability effects from EM and BTI induced failures at the circuit, architecture and system levels of abstraction. Readers will benefit from a focus on topics such as recently developed, physics-based EM modeling, EM modeling for multi-segment wires, new EM-aware power grid analysis, and system level EM-induced reliability optimization and management techniques. Reviews classic Electromigration (EM) models, as well as existing EM failure models and discusses the limitations of those models; Introduces a dynamic EM model to address transient stress evolution, in which wires are stressed under time-varying current flows, and the EM recovery effects. Also includes new, parameterized equivalent DC current based EM models to address the recovery and transient effects; Presents a cross-layer approach to transistor aging modeling, analysis and mitigation, spanning multiple abstraction levels; Equips readers for EM-induced dynamic reliability management and energy or lifetime optimization techniques, for many-core dark silicon microprocessors, embedded systems, lower power many-core processors and datacenters.
ISBN: 9783030261726
Standard No.: 10.1007/978-3-030-26172-6doiSubjects--Topical Terms:
563332
Electronic circuits.
LC Class. No.: TK7867-7867.5
Dewey Class. No.: 621.3815
Long-Term Reliability of Nanometer VLSI Systems = Modeling, Analysis and Optimization /
LDR
:04549nam a22004095i 4500
001
1010267
003
DE-He213
005
20200706084305.0
007
cr nn 008mamaa
008
210106s2019 gw | s |||| 0|eng d
020
$a
9783030261726
$9
978-3-030-26172-6
024
7
$a
10.1007/978-3-030-26172-6
$2
doi
035
$a
978-3-030-26172-6
050
4
$a
TK7867-7867.5
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
072
7
$a
TJFC
$2
thema
072
7
$a
TJFD
$2
thema
082
0 4
$a
621.3815
$2
23
100
1
$a
Tan, Sheldon.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
686626
245
1 0
$a
Long-Term Reliability of Nanometer VLSI Systems
$h
[electronic resource] :
$b
Modeling, Analysis and Optimization /
$c
by Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr.
250
$a
1st ed. 2019.
264
1
$a
Cham :
$b
Springer International Publishing :
$b
Imprint: Springer,
$c
2019.
300
$a
XLI, 460 p. 211 illus., 195 illus. in color.
$b
online resource.
336
$a
text
$b
txt
$2
rdacontent
337
$a
computer
$b
c
$2
rdamedia
338
$a
online resource
$b
cr
$2
rdacarrier
347
$a
text file
$b
PDF
$2
rda
505
0
$a
Part I. New physics-based EM analysis and system-level dynamic reliability management -- Chapter 1. Introduction -- Chapter 2. Physics Based EM Modeling -- Chapter 3. Fast EM Stress Evolution Analysis Using Krylov Subspace Method -- Chapter 4. Fast EM Immortatlity Analysis For Multisegment Copper Interconnect Wires -- Chapter 5. Dynamic EM Models For Transient Stress Evolution and Recovery -- Chapter 6. Compact EM Models for Multi-SEgment Interconnect Wires -- Chapter 7. EM Assesment for Power Grid Networks -- Chapter 8. Resource Based EM Modeling for Multi-Crore Microprocessors -- Chapter 9. DRM and Optimization for Real Time Embedded Systems -- Chapter 10. Learning Based DRM and Energy Optimization for Many Core Dark Silicaon Processors -- Chapter 11. Recovery Aware DRM for Near Threshold Dark Silicon Processors -- Chapter 12. Cross-Layer DRM and Optimization For Datacenter Systems -- Part II. Transistor Aging Effects and Reliability -- 13. Introduction -- Chapter 14. Aging AWare Timings Analysis -- Chapter 15. Aging Aware Standard Cell Library Optimization Methods -- Chapter 16. Aging Effects In Sequential Elements -- Chapter 17. Aging Guardband Reduction Through Selective Flip Flop Optimization -- Chapter 18. Workload Aware Static Aging Monitoring and Mitigation of Timing Critical Flip Flops -- Chapter 19. Aging Relaxation at Micro Architecture Level Using Special NOPS -- Chapter 20. Extratime Modelling and Analyis of Transistor Agin at Microarchitecture Level -- Chapter 21. Reducing Processor Wearout By Exploiting The Timing Slack of Instructions.
520
$a
This book provides readers with a detailed reference regarding two of the most important long-term reliability and aging effects on nanometer integrated systems, electromigrations (EM) for interconnect and biased temperature instability (BTI) for CMOS devices. The authors discuss in detail recent developments in the modeling, analysis and optimization of the reliability effects from EM and BTI induced failures at the circuit, architecture and system levels of abstraction. Readers will benefit from a focus on topics such as recently developed, physics-based EM modeling, EM modeling for multi-segment wires, new EM-aware power grid analysis, and system level EM-induced reliability optimization and management techniques. Reviews classic Electromigration (EM) models, as well as existing EM failure models and discusses the limitations of those models; Introduces a dynamic EM model to address transient stress evolution, in which wires are stressed under time-varying current flows, and the EM recovery effects. Also includes new, parameterized equivalent DC current based EM models to address the recovery and transient effects; Presents a cross-layer approach to transistor aging modeling, analysis and mitigation, spanning multiple abstraction levels; Equips readers for EM-induced dynamic reliability management and energy or lifetime optimization techniques, for many-core dark silicon microprocessors, embedded systems, lower power many-core processors and datacenters.
650
0
$a
Electronic circuits.
$3
563332
650
0
$a
Microprocessors.
$3
632481
650
1 4
$a
Electronic Circuits and Devices.
$3
782968
650
2 4
$a
Circuits and Systems.
$3
670901
650
2 4
$a
Processor Architectures.
$3
669787
700
1
$a
Tahoori, Mehdi.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1304330
700
1
$a
Kim, Taeyoung.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1304331
700
1
$a
Wang, Shengcheng.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1304332
700
1
$a
Sun, Zeyu.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1304333
700
1
$a
Kiamehr, Saman.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1304334
710
2
$a
SpringerLink (Online service)
$3
593884
773
0
$t
Springer Nature eBook
776
0 8
$i
Printed edition:
$z
9783030261719
776
0 8
$i
Printed edition:
$z
9783030261733
776
0 8
$i
Printed edition:
$z
9783030261740
856
4 0
$u
https://doi.org/10.1007/978-3-030-26172-6
912
$a
ZDB-2-PHA
912
$a
ZDB-2-SXP
950
$a
Physics and Astronomy (SpringerNature-11651)
950
$a
Physics and Astronomy (R0) (SpringerNature-43715)
筆 0 讀者評論
多媒體
評論
新增評論
分享你的心得
Export
取書館別
處理中
...
變更密碼[密碼必須為2種組合(英文和數字)及長度為10碼以上]
登入