國立虎尾科技大學 |

Deep In-memory Architectures for Machine Learning

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Deep In-memory Architectures for Machine Learning/ by Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag.
作者:	Kang, Mingu.
其他作者:	Shanbhag, Naresh R.
面頁冊數:	X, 174 p. 104 illus., 65 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Processor Architectures. -
電子資源:	https://doi.org/10.1007/978-3-030-35971-3
ISBN:	9783030359713

Deep In-memory Architectures for Machine Learning
Kang, Mingu.

Deep In-memory Architectures for Machine Learning[electronic resource] /by Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag. - 1st ed. 2020. - X, 174 p. 104 illus., 65 illus. in color.online resource.

Introduction -- The Deep In-memory Architecture (DIMA) -- DIMA Prototype Integrated Circuits -- A Variation-Tolerant DIMA via On-Chip Training -- Mapping Inference Algorithms to DIMA -- PROMISE: A DIMA-based Accelerator -- Future Prospects -- Index.

This book describes the recent innovation of deep in-memory architectures for realizing AI systems that operate at the edge of energy-latency-accuracy trade-offs. From first principles to lab prototypes, this book provides a comprehensive view of this emerging topic for both the practicing engineer in industry and the researcher in academia. The book is a journey into the exciting world of AI systems in hardware. Describes deep in-memory architectures for AI systems from first principles, covering both circuit design and architectures; Discusses how DIMAs pushes the limits of energy-delay product of decision-making machines via its intrinsic energy-SNR trade-off; Offers readers a unique Shannon-inspired perspective to understand the system-level energy-accuracy trade-off and robustness in such architectures; Illustrates principles and design methods via case studies of actual integrated circuit prototypes with measured results in the laboratory; Presents DIMA's various models to evaluate DIMA's decision-making accuracy, energy, and latency trade-offs with various design parameter.

ISBN: 9783030359713

Standard No.: 10.1007/978-3-030-35971-3doiSubjects--Topical Terms:

669787
Processor Architectures.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Deep In-memory Architectures for Machine Learning
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