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Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies/ by António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta.
作者:	Canelas, António Manuel Lourenço.
其他作者:	Guilherme, Jorge Manuel Correia.
面頁冊數:	XXIII, 237 p. 139 illus., 97 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Electronic circuits. -
電子資源:	https://doi.org/10.1007/978-3-030-41536-5
ISBN:	9783030415365

Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies
Canelas, António Manuel Lourenço.

Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies[electronic resource] /by António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta. - 1st ed. 2020. - XXIII, 237 p. 139 illus., 97 illus. in color.online resource.

Introduction -- Analog IC Sizing Background -- Yield Estimation Techniques Related Work -- Monte Carlo-Based Yield Estimation New Methodology -- AIDA-C Variation-Aware Circuit Synthesis Tool -- Tests & Results -- Conclusion and Future Work -- Index.

This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations. The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization. Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms; Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow; Includes detailed background on automatic analog IC sizing and optimization.

ISBN: 9783030415365

Standard No.: 10.1007/978-3-030-41536-5doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies
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