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Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies/ by António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta.
作者:	Canelas, António Manuel Lourenço.
其他作者:	Horta, Nuno Cavaco Gomes.
面頁冊數:	XXIII, 237 p. 139 illus., 97 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Electronics and Microelectronics, Instrumentation. -
電子資源:	https://doi.org/10.1007/978-3-030-41536-5
ISBN:	9783030415365

Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies
Canelas, António Manuel Lourenço.

Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies[electronic resource] /by António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta. - 1st ed. 2020. - XXIII, 237 p. 139 illus., 97 illus. in color.online resource.

Introduction -- Analog IC Sizing Background -- Yield Estimation Techniques Related Work -- Monte Carlo-Based Yield Estimation New Methodology -- AIDA-C Variation-Aware Circuit Synthesis Tool -- Tests & Results -- Conclusion and Future Work -- Index.

This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations. The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization. Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms; Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow; Includes detailed background on automatic analog IC sizing and optimization.

ISBN: 9783030415365

Standard No.: 10.1007/978-3-030-41536-5doiSubjects--Topical Terms:

670219
Electronics and Microelectronics, Instrumentation.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies
LDR:02983nam a22003975i 4500 001 1023103
003 DE-He213
005 20200701083005.0
007 cr nn 008mamaa
008 210318s2020 gw | s |||| 0|eng d
020 $a 9783030415365 $9 978-3-030-41536-5
024 7 $a 10.1007/978-3-030-41536-5 $2 doi
035 $a 978-3-030-41536-5
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Canelas, António Manuel Lourenço. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1318973
245 1 0 $a Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies $h [electronic resource] / $c by António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta.
250 $a 1st ed. 2020.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2020.
300 $a XXIII, 237 p. 139 illus., 97 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a Introduction -- Analog IC Sizing Background -- Yield Estimation Techniques Related Work -- Monte Carlo-Based Yield Estimation New Methodology -- AIDA-C Variation-Aware Circuit Synthesis Tool -- Tests & Results -- Conclusion and Future Work -- Index.
520 $a This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations. The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization. Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms; Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow; Includes detailed background on automatic analog IC sizing and optimization.
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
650 2 4 $a Cyber-physical systems, IoT. $3 1226036
650 1 4 $a Circuits and Systems. $3 670901
650 0 $a Microelectronics. $3 554956
650 0 $a Electronics. $3 596389
650 0 $a Embedded computer systems. $3 562313
650 0 $a Internet of things. $3 1023130
650 0 $a Computer engineering. $3 569006
650 0 $a Electronic circuits. $3 563332
700 1 $a Horta, Nuno Cavaco Gomes. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1301261
700 1 $a Guilherme, Jorge Manuel Correia. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1318974
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783030415358
776 0 8 $i Printed edition: $z 9783030415372
776 0 8 $i Printed edition: $z 9783030415389
856 4 0 $u https://doi.org/10.1007/978-3-030-41536-5
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)