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A Pipelined Multi-Core Machine with Operating System Support = Hardware Implementation and Correctness Proof /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	A Pipelined Multi-Core Machine with Operating System Support/ by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul.
Reminder of title:	Hardware Implementation and Correctness Proof /
Author:	Lutsyk, Petro.
other author:	Oberhauser, Jonas.
Description:	XV, 628 p. 1 illus.online resource. :
Contained By:	Springer Nature eBook
Subject:	Computer programming. -
Online resource:	https://doi.org/10.1007/978-3-030-43243-0
ISBN:	9783030432430

A Pipelined Multi-Core Machine with Operating System Support = Hardware Implementation and Correctness Proof /
Lutsyk, Petro.

A Pipelined Multi-Core Machine with Operating System SupportHardware Implementation and Correctness Proof /[electronic resource] :by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul. - 1st ed. 2020. - XV, 628 p. 1 illus.online resource. - Theoretical Computer Science and General Issues ;9999. - Theoretical Computer Science and General Issues ;9163.

Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic.

This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk .

ISBN: 9783030432430

Standard No.: 10.1007/978-3-030-43243-0doiSubjects--Topical Terms:

527822
Computer programming.

LC Class. No.: QA76.6-76.66

Dewey Class. No.: 005.11

A Pipelined Multi-Core Machine with Operating System Support = Hardware Implementation and Correctness Proof /
LDR:02713nam a22004095i 4500 001 1025800
003 DE-He213
005 20200703111002.0
007 cr nn 008mamaa
008 210318s2020 gw | s |||| 0|eng d
020 $a 9783030432430 $9 978-3-030-43243-0
024 7 $a 10.1007/978-3-030-43243-0 $2 doi
035 $a 978-3-030-43243-0
050 4 $a QA76.6-76.66
072 7 $a UM $2 bicssc
072 7 $a COM051000 $2 bisacsh
072 7 $a UM $2 thema
082 0 4 $a 005.11 $2 23
100 1 $a Lutsyk, Petro. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1269637
245 1 2 $a A Pipelined Multi-Core Machine with Operating System Support $h [electronic resource] : $b Hardware Implementation and Correctness Proof / $c by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul.
250 $a 1st ed. 2020.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2020.
300 $a XV, 628 p. 1 illus. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
490 1 $a Theoretical Computer Science and General Issues ; $v 9999
505 0 $a Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic.
520 $a This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk .
650 0 $a Computer programming. $3 527822
650 0 $a Computer organization. $3 596298
650 0 $a Microprogramming . $3 1257366
650 0 $a Input-output equipment (Computers). $3 1254918
650 0 $a Artificial intelligence. $3 559380
650 0 $a Computer logic. $3 786340
650 0 $a Computers. $3 565115
650 1 4 $a Programming Techniques. $3 669781
650 2 4 $a Computer Systems Organization and Communication Networks. $3 669309
650 2 4 $a Control Structures and Microprogramming. $3 669788
650 2 4 $a Input/Output and Data Communications. $3 669873
650 2 4 $a Logic in AI. $3 1228083
650 2 4 $a Theory of Computation. $3 669322
700 1 $a Oberhauser, Jonas. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1322122
700 1 $a Paul, Wolfgang J. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1114511
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783030432423
776 0 8 $i Printed edition: $z 9783030432447
830 0 $a Theoretical Computer Science and General Issues ; $v 9163 $3 1253524
856 4 0 $u https://doi.org/10.1007/978-3-030-43243-0
912 $a ZDB-2-SCS
912 $a ZDB-2-SXCS
912 $a ZDB-2-LNC
950 $a Computer Science (SpringerNature-11645)
950 $a Computer Science (R0) (SpringerNature-43710)