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A Pipelined Multi-Core Machine with Operating System Support = Hardware Implementation and Correctness Proof /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	A Pipelined Multi-Core Machine with Operating System Support/ by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul.
其他題名:	Hardware Implementation and Correctness Proof /
作者:	Lutsyk, Petro.
其他作者:	Paul, Wolfgang J.
面頁冊數:	XV, 628 p. 1 illus.online resource. :
Contained By:	Springer Nature eBook
標題:	Theory of Computation. -
電子資源:	https://doi.org/10.1007/978-3-030-43243-0
ISBN:	9783030432430

A Pipelined Multi-Core Machine with Operating System Support = Hardware Implementation and Correctness Proof /
Lutsyk, Petro.

A Pipelined Multi-Core Machine with Operating System SupportHardware Implementation and Correctness Proof /[electronic resource] :by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul. - 1st ed. 2020. - XV, 628 p. 1 illus.online resource. - Theoretical Computer Science and General Issues ;9999. - Theoretical Computer Science and General Issues ;9163.

Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic.

This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk .

ISBN: 9783030432430

Standard No.: 10.1007/978-3-030-43243-0doiSubjects--Topical Terms:

669322
Theory of Computation.

LC Class. No.: QA76.6-76.66

Dewey Class. No.: 005.11

A Pipelined Multi-Core Machine with Operating System Support = Hardware Implementation and Correctness Proof /
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