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Hardware Architectures for Post-Quan...
~
Karri, Ramesh.
Hardware Architectures for Post-Quantum Digital Signature Schemes
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Hardware Architectures for Post-Quantum Digital Signature Schemes/ by Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marc Manzano, Ramesh Karri.
作者:
Soni, Deepraj.
其他作者:
Karri, Ramesh.
面頁冊數:
XXII, 170 p. 68 illus., 66 illus. in color.online resource. :
Contained By:
Springer Nature eBook
標題:
Processor Architectures. -
電子資源:
https://doi.org/10.1007/978-3-030-57682-0
ISBN:
9783030576820
Hardware Architectures for Post-Quantum Digital Signature Schemes
Soni, Deepraj.
Hardware Architectures for Post-Quantum Digital Signature Schemes
[electronic resource] /by Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marc Manzano, Ramesh Karri. - 1st ed. 2021. - XXII, 170 p. 68 illus., 66 illus. in color.online resource.
Introduction -- qTESLA -- CRYSTALS –Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions.
This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.
ISBN: 9783030576820
Standard No.: 10.1007/978-3-030-57682-0doiSubjects--Topical Terms:
669787
Processor Architectures.
LC Class. No.: TK7888.4
Dewey Class. No.: 621.3815
Hardware Architectures for Post-Quantum Digital Signature Schemes
LDR
:02499nam a22003975i 4500
001
1046289
003
DE-He213
005
20211028131952.0
007
cr nn 008mamaa
008
220103s2021 sz | s |||| 0|eng d
020
$a
9783030576820
$9
978-3-030-57682-0
024
7
$a
10.1007/978-3-030-57682-0
$2
doi
035
$a
978-3-030-57682-0
050
4
$a
TK7888.4
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
072
7
$a
TJFC
$2
thema
082
0 4
$a
621.3815
$2
23
100
1
$a
Soni, Deepraj.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1349820
245
1 0
$a
Hardware Architectures for Post-Quantum Digital Signature Schemes
$h
[electronic resource] /
$c
by Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marc Manzano, Ramesh Karri.
250
$a
1st ed. 2021.
264
1
$a
Cham :
$b
Springer International Publishing :
$b
Imprint: Springer,
$c
2021.
300
$a
XXII, 170 p. 68 illus., 66 illus. in color.
$b
online resource.
336
$a
text
$b
txt
$2
rdacontent
337
$a
computer
$b
c
$2
rdamedia
338
$a
online resource
$b
cr
$2
rdacarrier
347
$a
text file
$b
PDF
$2
rda
505
0
$a
Introduction -- qTESLA -- CRYSTALS –Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions.
520
$a
This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.
650
2 4
$a
Processor Architectures.
$3
669787
650
2 4
$a
Cyber-physical systems, IoT.
$3
1226036
650
1 4
$a
Circuits and Systems.
$3
670901
650
0
$a
Microprocessors.
$3
632481
650
0
$a
Embedded computer systems.
$3
562313
650
0
$a
Internet of things.
$3
1023130
650
0
$a
Computer engineering.
$3
569006
650
0
$a
Electronic circuits.
$3
563332
700
1
$a
Karri, Ramesh.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1320196
700
1
$a
Manzano, Marc.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1349824
700
1
$a
Aaraj, Najwa.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1349823
700
1
$a
Nabeel, Mohammed.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1349822
700
1
$a
Basu, Kanad.
$e
author.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1349821
710
2
$a
SpringerLink (Online service)
$3
593884
773
0
$t
Springer Nature eBook
776
0 8
$i
Printed edition:
$z
9783030576813
776
0 8
$i
Printed edition:
$z
9783030576837
776
0 8
$i
Printed edition:
$z
9783030576844
856
4 0
$u
https://doi.org/10.1007/978-3-030-57682-0
912
$a
ZDB-2-ENG
912
$a
ZDB-2-SXE
950
$a
Engineering (SpringerNature-11647)
950
$a
Engineering (R0) (SpringerNature-43712)
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