國立虎尾科技大學 |

VLSI-SoC: Design Trends = 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	VLSI-SoC: Design Trends/ edited by Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis.
其他題名:	28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers /
其他作者:	Reis, Ricardo.
面頁冊數:	XVIII, 364 p. 209 illus., 139 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Information Systems Applications (incl. Internet). -
電子資源:	https://doi.org/10.1007/978-3-030-81641-4
ISBN:	9783030816414

VLSI-SoC: Design Trends = 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers /
VLSI-SoC: Design Trends28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers /[electronic resource] :edited by Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis. - 1st ed. 2021. - XVIII, 364 p. 209 illus., 139 illus. in color.online resource. - IFIP Advances in Information and Communication Technology,6211868-4238 ;. - IFIP Advances in Information and Communication Technology,449.

Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22nm FDSOI -- A 125 pJ/b Mixed-Mode MCMC MIMO Detector with Relaxed DSP -- Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring -- Fully-Autonomous SoC Synthesis using Customizable Cell-Based Analog and Mixed-signal Circuits Generation -- Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform -- SAT-Based Mapping of Data-Flow Graph onto Coarse-Grained Reconfigurable Array -- Learning Based Timing Closure on Relative Timed Design -- Multilevel Signalling for High-Speed Chiplet-to-Chiplet Communication -- From Informal Specifications to an ABV Framework for Industrial Firmware Verification -- Modular Functional Testing: Targeting the Small Embedded Memories in GPUs -- RAT: A Lightweight Architecture Independent System-level Soft Error Mitigation Technique -- SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption -- 3D Nanofabric: Layout Challenges and Solutions for Ultra-Scaled Logic Designs -- 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model -- Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics -- A Technology Backward-Compatible Compilation Flow for Processing-In-Memory.

This book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.* The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.

ISBN: 9783030816414

Standard No.: 10.1007/978-3-030-81641-4doiSubjects--Topical Terms:

881699
Information Systems Applications (incl. Internet).

LC Class. No.: QA76.9.C643

Dewey Class. No.: 004.6

VLSI-SoC: Design Trends = 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers /
LDR:04035nam a22004215i 4500 001 1047201
003 DE-He213
005 20210714182738.0
007 cr nn 008mamaa
008 220103s2021 gw | s |||| 0|eng d
020 $a 9783030816414 $9 978-3-030-81641-4
024 7 $a 10.1007/978-3-030-81641-4 $2 doi
035 $a 978-3-030-81641-4
050 4 $a QA76.9.C643
050 4 $a TK5105.5-5105.9
072 7 $a UT $2 bicssc
072 7 $a COM043000 $2 bisacsh
072 7 $a UT $2 thema
082 0 4 $a 004.6 $2 23
245 1 0 $a VLSI-SoC: Design Trends $h [electronic resource] : $b 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers / $c edited by Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis.
250 $a 1st ed. 2021.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2021.
300 $a XVIII, 364 p. 209 illus., 139 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
490 1 $a IFIP Advances in Information and Communication Technology, $x 1868-4238 ; $v 621
505 0 $a Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22nm FDSOI -- A 125 pJ/b Mixed-Mode MCMC MIMO Detector with Relaxed DSP -- Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring -- Fully-Autonomous SoC Synthesis using Customizable Cell-Based Analog and Mixed-signal Circuits Generation -- Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform -- SAT-Based Mapping of Data-Flow Graph onto Coarse-Grained Reconfigurable Array -- Learning Based Timing Closure on Relative Timed Design -- Multilevel Signalling for High-Speed Chiplet-to-Chiplet Communication -- From Informal Specifications to an ABV Framework for Industrial Firmware Verification -- Modular Functional Testing: Targeting the Small Embedded Memories in GPUs -- RAT: A Lightweight Architecture Independent System-level Soft Error Mitigation Technique -- SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption -- 3D Nanofabric: Layout Challenges and Solutions for Ultra-Scaled Logic Designs -- 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model -- Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics -- A Technology Backward-Compatible Compilation Flow for Processing-In-Memory.
520 $a This book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.* The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.
650 2 4 $a Information Systems Applications (incl. Internet). $3 881699
650 2 4 $a Input/Output and Data Communications. $3 669873
650 2 4 $a Control Structures and Microprogramming. $3 669788
650 1 4 $a Computer Systems Organization and Communication Networks. $3 669309
650 0 $a Application software. $3 528147
650 0 $a Input-output equipment (Computers). $3 1254918
650 0 $a Microprogramming . $3 1257366
650 0 $a Computer organization. $3 596298
700 1 $a Reis, Ricardo. $4 edt $4 http://id.loc.gov/vocabulary/relators/edt $3 677079
700 1 $a Kvatinsky, Shahar. $e editor. $1 https://orcid.org/0000-0001-7277-7271 $4 edt $4 http://id.loc.gov/vocabulary/relators/edt $3 1350871
700 1 $a Korgaonkar, Kunal. $e editor. $1 https://orcid.org/0000-0002-9078-2944 $4 edt $4 http://id.loc.gov/vocabulary/relators/edt $3 1350870
700 1 $a Gaillardon, Pierre-Emmanuel. $4 edt $4 http://id.loc.gov/vocabulary/relators/edt $3 891993
700 1 $a Calimera, Andrea. $e editor. $1 https://orcid.org/0000-0001-5881-3811 $4 edt $4 http://id.loc.gov/vocabulary/relators/edt $3 1350869
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783030816407
776 0 8 $i Printed edition: $z 9783030816421
776 0 8 $i Printed edition: $z 9783030816438
830 0 $a IFIP Advances in Information and Communication Technology, $x 1868-4238 ; $v 449 $3 1255091
856 4 0 $u https://doi.org/10.1007/978-3-030-81641-4
912 $a ZDB-2-SCS
912 $a ZDB-2-SXCS
950 $a Computer Science (SpringerNature-11645)
950 $a Computer Science (R0) (SpringerNature-43710)