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Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs/ by Alexandra Zimpeck, Cristina Meinhardt, Laurent Artola, Ricardo Reis.
作者:	Zimpeck, Alexandra.
其他作者:	Reis, Ricardo.
面頁冊數:	XIII, 131 p. 89 illus., 86 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Electronic Circuits and Devices. -
電子資源:	https://doi.org/10.1007/978-3-030-68368-9
ISBN:	9783030683689

Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs
Zimpeck, Alexandra.

Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs[electronic resource] /by Alexandra Zimpeck, Cristina Meinhardt, Laurent Artola, Ricardo Reis. - 1st ed. 2021. - XIII, 131 p. 89 illus., 86 illus. in color.online resource.

Chapter 1. Introduction -- Chapter 2. FinFET Technology -- Chapter 3. Reliability Challenges in FinFETs -- Chapter 4. Circuit-Level Mitigation Approaches -- Chapter 5. Evaluation Methodology -- Chapter 6. Process Variability Mitigation -- Chapter 7. Soft Error Mitigation -- Chapter 8. General Trade-offs -- Chapter 9. Final Remarks.

This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section. Explains how to measure the influence of process variability (e.g. work-function fluctuations) and radiation-induced soft errors in FinFET logic cells; Enables designers to improve the robustness of FinFET integrated circuits without focusing on manufacturing adjustments; Discusses the benefits and downsides of using circuit-level approaches such as transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor for mitigating the impact of process variability and soft errors; Evaluates the techniques described in the context of different test scenarios: distinct levels of process variations, transistor sizing, and different radiation features; Helps readers identify the best circuit design considering the target application and design requirements like area constraints or power/delay limitations.

ISBN: 9783030683689

Standard No.: 10.1007/978-3-030-68368-9doiSubjects--Topical Terms:

782968
Electronic Circuits and Devices.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs
LDR:03665nam a22003975i 4500 001 1047573
003 DE-He213
005 20211124222334.0
007 cr nn 008mamaa
008 220103s2021 sz | s |||| 0|eng d
020 $a 9783030683689 $9 978-3-030-68368-9
024 7 $a 10.1007/978-3-030-68368-9 $2 doi
035 $a 978-3-030-68368-9
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Zimpeck, Alexandra. $e author. $0 (orcid)0000-0002-3583-1002 $1 https://orcid.org/0000-0002-3583-1002 $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1351300
245 1 0 $a Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs $h [electronic resource] / $c by Alexandra Zimpeck, Cristina Meinhardt, Laurent Artola, Ricardo Reis.
250 $a 1st ed. 2021.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2021.
300 $a XIII, 131 p. 89 illus., 86 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a Chapter 1. Introduction -- Chapter 2. FinFET Technology -- Chapter 3. Reliability Challenges in FinFETs -- Chapter 4. Circuit-Level Mitigation Approaches -- Chapter 5. Evaluation Methodology -- Chapter 6. Process Variability Mitigation -- Chapter 7. Soft Error Mitigation -- Chapter 8. General Trade-offs -- Chapter 9. Final Remarks.
520 $a This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section. Explains how to measure the influence of process variability (e.g. work-function fluctuations) and radiation-induced soft errors in FinFET logic cells; Enables designers to improve the robustness of FinFET integrated circuits without focusing on manufacturing adjustments; Discusses the benefits and downsides of using circuit-level approaches such as transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor for mitigating the impact of process variability and soft errors; Evaluates the techniques described in the context of different test scenarios: distinct levels of process variations, transistor sizing, and different radiation features; Helps readers identify the best circuit design considering the target application and design requirements like area constraints or power/delay limitations.
650 2 4 $a Electronic Circuits and Devices. $3 782968
650 1 4 $a Circuits and Systems. $3 670901
650 0 $a Electronic circuits. $3 563332
700 1 $a Reis, Ricardo. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 677079
700 1 $a Artola, Laurent. $e author. $1 https://orcid.org/0000-0003-0730-7518 $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1351302
700 1 $a Meinhardt, Cristina. $e author. $1 https://orcid.org/0000-0003-1088-1000 $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1351301
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783030683672
776 0 8 $i Printed edition: $z 9783030683696
776 0 8 $i Printed edition: $z 9783030683702
856 4 0 $u https://doi.org/10.1007/978-3-030-68368-9
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)