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Dual Mode Logic = A New Paradigm for Digital IC Design /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Dual Mode Logic/ by Itamar Levi, Alexander Fish.
Reminder of title:	A New Paradigm for Digital IC Design /
Author:	Levi, Itamar.
other author:	Fish, Alexander.
Description:	XIV, 185 p. 111 illus., 68 illus. in color.online resource. :
Contained By:	Springer Nature eBook
Subject:	Electronic circuits. -
Online resource:	https://doi.org/10.1007/978-3-030-40786-5
ISBN:	9783030407865

Dual Mode Logic = A New Paradigm for Digital IC Design /
Levi, Itamar.

Dual Mode LogicA New Paradigm for Digital IC Design /[electronic resource] :by Itamar Levi, Alexander Fish. - 1st ed. 2021. - XIV, 185 p. 111 illus., 68 illus. in color.online resource.

Chapter 1. Introduction -- Chapter 2. Introduction to Dual Mode Logic (DML) -- Chapter 3. Optimization of DML Gates -- Chapter 4. Low Voltage DML -- Chapter 5. DML Energy-Delay Tradeoffs and Optimization -- Chapter 6. DML Control -- Chapter 7. Towards a DML Library Characterization and Design with Standard Flow -- Chapter 8. Towards a DML Optimized Synthesis -- Chapter 9. Dual Mode Logic in FD-SOI Technology. Chapter 10. Conclusion.

This book presents Dual Mode Logic (DML), a new design paradigm for digital integrated circuits. DML logic gates can operate in two modes, each optimized for a different metric. Its on-the-fly switching between these operational modes at the gate, block and system levels provide maximal E-D optimization flexibility. Each highly detailed chapter has multiple illustrations showing how the DML paradigm seamlessly implements digital circuits that dissipate less energy while simultaneously improving performance and reducing area without a significant compromise in reliability. All the facets of the DML methodology are covered, starting from basic concepts, through single gate optimization, general module optimization, design trade-offs and new ways DML can be integrated into standard design flows using standard EDA tools. DML logic is compatible with numerous applications but is particularly advantageous for ultra-low power, reliable high performance systems, and advanced scaled technologies Written in language accessible to students and design engineers, each topic is oriented toward immediate application by all those interested in an alternative to CMOS logic. Describes a novel, promising alternative to conventional CMOS logic, known as Dual Mode Logic (DML), with which a single gate can be operated selectively in two modes, each optimized for a different metric (e.g., energy consumption, performance, size); Demonstrates several techniques at the architectural level, which can result in high energy savings and improved system performance; Focuses on the tradeoffs between power, area and speed including optimizations at the transistor and gate level, including alternatives to DML basic cells; Illustrates DML efficiency for a variety of VLSI applications.

ISBN: 9783030407865

Standard No.: 10.1007/978-3-030-40786-5doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Dual Mode Logic = A New Paradigm for Digital IC Design /
LDR:03566nam a22003975i 4500 001 1050743
003 DE-He213
005 20211119071241.0
007 cr nn 008mamaa
008 220103s2021 sz | s |||| 0|eng d
020 $a 9783030407865 $9 978-3-030-40786-5
024 7 $a 10.1007/978-3-030-40786-5 $2 doi
035 $a 978-3-030-40786-5
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Levi, Itamar. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1355125
245 1 0 $a Dual Mode Logic $h [electronic resource] : $b A New Paradigm for Digital IC Design / $c by Itamar Levi, Alexander Fish.
250 $a 1st ed. 2021.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2021.
300 $a XIV, 185 p. 111 illus., 68 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a Chapter 1. Introduction -- Chapter 2. Introduction to Dual Mode Logic (DML) -- Chapter 3. Optimization of DML Gates -- Chapter 4. Low Voltage DML -- Chapter 5. DML Energy-Delay Tradeoffs and Optimization -- Chapter 6. DML Control -- Chapter 7. Towards a DML Library Characterization and Design with Standard Flow -- Chapter 8. Towards a DML Optimized Synthesis -- Chapter 9. Dual Mode Logic in FD-SOI Technology. Chapter 10. Conclusion.
520 $a This book presents Dual Mode Logic (DML), a new design paradigm for digital integrated circuits. DML logic gates can operate in two modes, each optimized for a different metric. Its on-the-fly switching between these operational modes at the gate, block and system levels provide maximal E-D optimization flexibility. Each highly detailed chapter has multiple illustrations showing how the DML paradigm seamlessly implements digital circuits that dissipate less energy while simultaneously improving performance and reducing area without a significant compromise in reliability. All the facets of the DML methodology are covered, starting from basic concepts, through single gate optimization, general module optimization, design trade-offs and new ways DML can be integrated into standard design flows using standard EDA tools. DML logic is compatible with numerous applications but is particularly advantageous for ultra-low power, reliable high performance systems, and advanced scaled technologies Written in language accessible to students and design engineers, each topic is oriented toward immediate application by all those interested in an alternative to CMOS logic. Describes a novel, promising alternative to conventional CMOS logic, known as Dual Mode Logic (DML), with which a single gate can be operated selectively in two modes, each optimized for a different metric (e.g., energy consumption, performance, size); Demonstrates several techniques at the architectural level, which can result in high energy savings and improved system performance; Focuses on the tradeoffs between power, area and speed including optimizations at the transistor and gate level, including alternatives to DML basic cells; Illustrates DML efficiency for a variety of VLSI applications.
650 0 $a Electronic circuits. $3 563332
650 0 $a Logic design. $3 561473
650 0 $a Microprocessors. $3 632481
650 1 4 $a Circuits and Systems. $3 670901
650 2 4 $a Logic Design. $3 670915
650 2 4 $a Processor Architectures. $3 669787
700 1 $a Fish, Alexander. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1283451
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783030407858
776 0 8 $i Printed edition: $z 9783030407872
776 0 8 $i Printed edition: $z 9783030407889
856 4 0 $u https://doi.org/10.1007/978-3-030-40786-5
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)