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VLSI-SoC: Technology Advancement on SoC Design = 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4–8, 2021, Revised and Extended Selected Papers /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	VLSI-SoC: Technology Advancement on SoC Design/ edited by Victor Grimblatt, Chip Hong Chang, Ricardo Reis, Anupam Chattopadhyay, Andrea Calimera.
其他題名:	29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4–8, 2021, Revised and Extended Selected Papers /
其他作者:	Calimera, Andrea.
面頁冊數:	XIV, 267 p. 143 illus., 109 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Computer Hardware. -
電子資源:	https://doi.org/10.1007/978-3-031-16818-5
ISBN:	9783031168185

VLSI-SoC: Technology Advancement on SoC Design = 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4–8, 2021, Revised and Extended Selected Papers /
VLSI-SoC: Technology Advancement on SoC Design29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4–8, 2021, Revised and Extended Selected Papers /[electronic resource] :edited by Victor Grimblatt, Chip Hong Chang, Ricardo Reis, Anupam Chattopadhyay, Andrea Calimera. - 1st ed. 2022. - XIV, 267 p. 143 illus., 109 illus. in color.online resource. - IFIP Advances in Information and Communication Technology,6611868-422X ;. - IFIP Advances in Information and Communication Technology,449.

On the Efficiency of AdapTTA: an Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets -- Low-overhead Early-stopping Policies for Efficient Random Forests Inference on Microcontrollers -- Transformative Hardware Design following the Model-Driven Architecture Vision -- Exploiting program slicing and instruction clusterization to identify the cause of faulty temporal behaviours at system level -- A DfT Strategy for Detecting Emerging Faults in RRAMs -- FMEA on Critical Systems: a Cross-layer Approach based on High-Level Models -- Design and Mitigation techniques of Radiation induced SEEs on Open-Source Embedded Static RAMs -- Design of A Reconfigurable Optical Computing Architecture Using Phase Change Material -- END-TRUE: Emerging Nanotechnology-based Double-Throughput True Random Number Generator -- A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design -- A Regulated Sensing Solution based on a Self-Reference Principle for PCM+OTS Memory Array -- An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design.

This book contains extended and revised versions of the best papers presented at the 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, held in Singapore, in October 2021*. The 12 full papers included in this volume were carefully reviewed and selected from the 44 papers (out of 75 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.

ISBN: 9783031168185

Standard No.: 10.1007/978-3-031-16818-5doiSubjects--Topical Terms:

669779
Computer Hardware.

LC Class. No.: TK7885-7895

Dewey Class. No.: 621.39

VLSI-SoC: Technology Advancement on SoC Design = 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4–8, 2021, Revised and Extended Selected Papers /
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