國立虎尾科技大學 |

Completion Detection in Asynchronous Circuits = Toward Solution of Clock-Related Design Challenges /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Completion Detection in Asynchronous Circuits/ by Pallavi Srivastava.
其他題名:	Toward Solution of Clock-Related Design Challenges /
作者:	Srivastava, Pallavi.
面頁冊數:	XV, 119 p. 65 illus., 51 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Processor Architectures. -
電子資源:	https://doi.org/10.1007/978-3-031-18397-3
ISBN:	9783031183973

Completion Detection in Asynchronous Circuits = Toward Solution of Clock-Related Design Challenges /
Srivastava, Pallavi.

Completion Detection in Asynchronous CircuitsToward Solution of Clock-Related Design Challenges /[electronic resource] :by Pallavi Srivastava. - 1st ed. 2022. - XV, 119 p. 65 illus., 51 illus. in color.online resource.

Introduction to asynchronous circuit design -- "Preliminary considerations for asynchronous circuit design." -- "Completion detection schemes for asynchronous design style" -- Case Studies: Barrel shifter and binary adders -- "Generic Architecture of deterministic completion detection scheme" -- Architecture optimization using deterministic completion detection" -- Simulations.

This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits. Analyzes circuit design techniques in the context of timing constraints; Develops a generic, deterministic completion detection scheme for asynchronous circuits using bundled data protocol; Demonstrates a single-precision, asynchronous bundled data barrel shifter to validate the completion detection scheme.

ISBN: 9783031183973

Standard No.: 10.1007/978-3-031-18397-3doiSubjects--Topical Terms:

669787
Processor Architectures.

LC Class. No.: TK7867-7867.5

Dewey Class. No.: 621.3815

Completion Detection in Asynchronous Circuits = Toward Solution of Clock-Related Design Challenges /
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