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A Primer on Memory Persistency

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	A Primer on Memory Persistency/ by Gogte Vaibhav, Kolli Aasheesh, Wenisch Thomas F.
作者:	Vaibhav, Gogte.
其他作者:	Thomas F., Wenisch.
面頁冊數:	XIX, 95 p.online resource. :
Contained By:	Springer Nature eBook
標題:	Processor Architectures. -
電子資源:	https://doi.org/10.1007/978-3-031-79205-2
ISBN:	9783031792052

A Primer on Memory Persistency
Vaibhav, Gogte.

A Primer on Memory Persistency[electronic resource] /by Gogte Vaibhav, Kolli Aasheesh, Wenisch Thomas F. - 1st ed. 2022. - XIX, 95 p.online resource. - Synthesis Lectures on Computer Architecture,1935-3243. - Synthesis Lectures on Computer Architecture,.

Preface -- Acknowledgments -- Persistent Memories -- Data Persistence -- Memory Persistency Models -- Hardware Mechanisms for Atomic Durability -- Programming Persistent Memory Systems -- Conclusion -- Bibliography -- Authors' Biographies.

This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.

ISBN: 9783031792052

Standard No.: 10.1007/978-3-031-79205-2doiSubjects--Topical Terms:

669787
Processor Architectures.

LC Class. No.: TK7867-7867.5

Dewey Class. No.: 621.3815

A Primer on Memory Persistency
LDR:03654nam a22003855i 4500 001 1086963
003 DE-He213
005 20220601135536.0
007 cr nn 008mamaa
008 221228s2022 sz | s |||| 0|eng d
020 $a 9783031792052 $9 978-3-031-79205-2
024 7 $a 10.1007/978-3-031-79205-2 $2 doi
035 $a 978-3-031-79205-2
050 4 $a TK7867-7867.5
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Vaibhav, Gogte. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1393866
245 1 2 $a A Primer on Memory Persistency $h [electronic resource] / $c by Gogte Vaibhav, Kolli Aasheesh, Wenisch Thomas F.
250 $a 1st ed. 2022.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2022.
300 $a XIX, 95 p. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
490 1 $a Synthesis Lectures on Computer Architecture, $x 1935-3243
505 0 $a Preface -- Acknowledgments -- Persistent Memories -- Data Persistence -- Memory Persistency Models -- Hardware Mechanisms for Atomic Durability -- Programming Persistent Memory Systems -- Conclusion -- Bibliography -- Authors' Biographies.
520 $a This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.
650 2 4 $a Processor Architectures. $3 669787
650 1 4 $a Electronic Circuits and Systems. $3 1366689
650 0 $a Computer architecture. $3 528145
650 0 $a Microprocessors. $3 632481
650 0 $a Electronic circuits. $3 563332
700 1 $a Thomas F., Wenisch. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1393868
700 1 $a Aasheesh, Kolli. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1393867
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783031792175
776 0 8 $i Printed edition: $z 9783031791932
776 0 8 $i Printed edition: $z 9783031792298
830 0 $a Synthesis Lectures on Computer Architecture, $x 1935-3243 $3 1393869
856 4 0 $u https://doi.org/10.1007/978-3-031-79205-2
912 $a ZDB-2-SXSC
950 $a Synthesis Collection of Technology (R0) (SpringerNature-85007)