國立虎尾科技大學 |

Resource efficient LDPC decoders = from algorithms to hardware architectures /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Resource efficient LDPC decoders/ Vikram Arkalgud Chandrasetty.
其他題名:	from algorithms to hardware architectures /
作者:	Chandrasetty, Vikram Arkalgud.
其他作者:	Aziz, Sayed Mahfuzul.
出版者:	Amsterdam :Academic Press, : 2018.,
面頁冊數:	1 online resource.
標題:	Digital communications. -
電子資源:	https://www.sciencedirect.com/science/book/9780128112557
ISBN:	9780128112564 (electronic bk.)

Resource efficient LDPC decoders = from algorithms to hardware architectures /
Chandrasetty, Vikram Arkalgud.

Resource efficient LDPC decodersfrom algorithms to hardware architectures /[electronic resource] :Vikram Arkalgud Chandrasetty. - Amsterdam :Academic Press,2018. - 1 online resource.

Includes bibliographical references and index.

1.Introduction 2. Overview of LDPC codes 3. Structure and flexibility of LDPC codes 4. LDPC decoding algorithms 5. LDPC decoder architectures 6. Hardware implementation of LDPC decoder 7. LDPC decoders in multimedia communication References 8. Prospective LDPC applications Appendix-A : Sample C-Programs and MATLAB models for LDPC code construction and simulation Appendix-B : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architecture Appendix-C : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture.

ISBN: 9780128112564 (electronic bk.)

Nat. Bib. No.: GBB7M5430bnbSubjects--Topical Terms:

562978
Digital communications.
Index Terms--Genre/Form:

554714
Electronic books.

LC Class. No.: TK7872.D37

Dewey Class. No.: 621.38932

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