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Transactional Memory, Second Edition

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Transactional Memory, Second Edition/ by Tim Harris, James Larus, Ravi Rajwar.
作者:	Harris, Tim.
其他作者:	Rajwar, Ravi.
面頁冊數:	XV, 247 p.online resource. :
Contained By:	Springer Nature eBook
標題:	Processor Architectures. -
電子資源:	https://doi.org/10.1007/978-3-031-01728-5
ISBN:	9783031017285

Transactional Memory, Second Edition
Harris, Tim.

Transactional Memory, Second Edition[electronic resource] /by Tim Harris, James Larus, Ravi Rajwar. - 1st ed. 2010. - XV, 247 p.online resource. - Synthesis Lectures on Computer Architecture,1935-3243. - Synthesis Lectures on Computer Architecture,.

Introduction -- Basic Transactions -- Building on Basic Transactions -- Software Transactional Memory -- Hardware-Supported Transactional Memory -- Conclusions.

The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010. Table of Contents: Introduction / Basic Transactions / Building on Basic Transactions / Software Transactional Memory / Hardware-Supported Transactional Memory / Conclusions.

ISBN: 9783031017285

Standard No.: 10.1007/978-3-031-01728-5doiSubjects--Topical Terms:

669787
Processor Architectures.

LC Class. No.: TK7867-7867.5

Dewey Class. No.: 621.3815

Transactional Memory, Second Edition
LDR:02876nam a22003735i 4500 001 1097458
003 DE-He213
005 20220601135901.0
007 cr nn 008mamaa
008 230315s2010 sz | s |||| 0|eng d
020 $a 9783031017285 $9 978-3-031-01728-5
024 7 $a 10.1007/978-3-031-01728-5 $2 doi
035 $a 978-3-031-01728-5
050 4 $a TK7867-7867.5
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Harris, Tim. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1407302
245 1 0 $a Transactional Memory, Second Edition $h [electronic resource] / $c by Tim Harris, James Larus, Ravi Rajwar.
250 $a 1st ed. 2010.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2010.
300 $a XV, 247 p. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
490 1 $a Synthesis Lectures on Computer Architecture, $x 1935-3243
505 0 $a Introduction -- Basic Transactions -- Building on Basic Transactions -- Software Transactional Memory -- Hardware-Supported Transactional Memory -- Conclusions.
520 $a The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010. Table of Contents: Introduction / Basic Transactions / Building on Basic Transactions / Software Transactional Memory / Hardware-Supported Transactional Memory / Conclusions.
650 2 4 $a Processor Architectures. $3 669787
650 1 4 $a Electronic Circuits and Systems. $3 1366689
650 0 $a Computer architecture. $3 528145
650 0 $a Microprocessors. $3 632481
650 0 $a Electronic circuits. $3 563332
700 1 $a Rajwar, Ravi. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 598629
700 1 $a Larus, James. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1407303
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783031006005
776 0 8 $i Printed edition: $z 9783031028564
830 0 $a Synthesis Lectures on Computer Architecture, $x 1935-3243 $3 1393869
856 4 0 $u https://doi.org/10.1007/978-3-031-01728-5
912 $a ZDB-2-SXSC
950 $a Synthesis Collection of Technology (R0) (SpringerNature-85007)