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基於嵌入式可規劃邏輯架構實現硬體加速應用於遠程光電容積脈波演算法 = =...
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陳玉林
基於嵌入式可規劃邏輯架構實現硬體加速應用於遠程光電容積脈波演算法 = = Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture /
Record Type:
Language materials, printed : Monograph/item
Title/Author:
基於嵌入式可規劃邏輯架構實現硬體加速應用於遠程光電容積脈波演算法 =/ 陳玉林.
Reminder of title:
Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture /
remainder title:
Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture.
Author:
陳玉林
Published:
雲林縣 :國立虎尾科技大學 , : 民113.07.,
Description:
[8], 53面 :圖, 表 ; : 30公分.;
Notes:
指導教授: 林光浩.
Subject:
嵌入式系統. -
Online resource:
電子資源
基於嵌入式可規劃邏輯架構實現硬體加速應用於遠程光電容積脈波演算法 = = Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture /
陳玉林
基於嵌入式可規劃邏輯架構實現硬體加速應用於遠程光電容積脈波演算法 =
Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture /Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture.陳玉林. - 初版. - 雲林縣 :國立虎尾科技大學 ,民113.07. - [8], 53面 :圖, 表 ;30公分.
指導教授: 林光浩.
碩士論文--國立虎尾科技大學電機工程系碩士班.
含參考書目.
遠程光電容積脈波(rPPG)技術是一種無接觸、非侵入式的方法,用於提取人體的生理訊號,如心率和血氧濃度等。由於 rPPG 需要處理高分辨率影像並從中提取微小的生理變化訊號,傳統的軟體方法在計算效率和即時性方面面臨挑戰。在本文中,提出一種基於嵌入式可程式邏輯架構(例如 AMD kria kv260)的硬體加速平台,用於優化 rPPG 演算法的執行效率。 本論文設計並實現一個專用硬體加速器,涵蓋數據訊號預處理、平面正交於皮膚(POS)演算法以及後續的訊號過濾處理。與傳統軟體實現相比,這種硬體加速方案在計算效率、即時性和功耗方面具有顯著優勢。實驗結果顯示,使用HRPA硬體加速器,rPPG訊號的處理速度提高13倍,並且在保持高準確度的同時,顯著降低處理延遲。.
(平裝)Subjects--Topical Terms:
995141
嵌入式系統.
基於嵌入式可規劃邏輯架構實現硬體加速應用於遠程光電容積脈波演算法 = = Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture /
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基於嵌入式可規劃邏輯架構實現硬體加速應用於遠程光電容積脈波演算法 =
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Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture /
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陳玉林.
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Implementation of Hardware Acceleration for rPPG Algorithm Based on Embedded Programmable Logic Architecture.
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初版.
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雲林縣 :
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國立虎尾科技大學 ,
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民113.07.
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[8], 53面 :
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圖, 表 ;
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指導教授: 林光浩.
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學年度: 112.
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碩士論文--國立虎尾科技大學電機工程系碩士班.
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含參考書目.
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遠程光電容積脈波(rPPG)技術是一種無接觸、非侵入式的方法,用於提取人體的生理訊號,如心率和血氧濃度等。由於 rPPG 需要處理高分辨率影像並從中提取微小的生理變化訊號,傳統的軟體方法在計算效率和即時性方面面臨挑戰。在本文中,提出一種基於嵌入式可程式邏輯架構(例如 AMD kria kv260)的硬體加速平台,用於優化 rPPG 演算法的執行效率。 本論文設計並實現一個專用硬體加速器,涵蓋數據訊號預處理、平面正交於皮膚(POS)演算法以及後續的訊號過濾處理。與傳統軟體實現相比,這種硬體加速方案在計算效率、即時性和功耗方面具有顯著優勢。實驗結果顯示,使用HRPA硬體加速器,rPPG訊號的處理速度提高13倍,並且在保持高準確度的同時,顯著降低處理延遲。.
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Remote photoplethysmography (rPPG) technology is a contactless, non-invasive method used to extract physiological signals such as heart rate and blood oxygen concentration from the human body. Due to the need to process high-resolution images and extract subtle physiological signal changes, traditional software-based methods face challenges in terms of computational efficiency and real-time performance. In this paper, we propose a hardware acceleration platform based on an embedded programmable logic architecture (e.g., AMD kria kv260) to optimize the execution efficiency of rPPG algorithms. We designed and implemented a dedicated hardware accelerator that encompasses data signal preprocessing, the rPPG algorithm(plane orthogonal to skin (POS) algorithm), and subsequent signal filtering processing. Compared to traditional software implementations, this hardware acceleration scheme offers significant advantages in terms of computational efficiency, real-time performance, and power consumption. Experimental results show that with HRPA (Hardware rPPG POS Accelerator), the processing speed of rPPG signals increased by 13 times, while maintaining high accuracy and significantly reducing processing latency..
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嵌入式系統.
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硬體加速.
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可程式邏輯架構.
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遠程光電容積脈波.
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hardware acceleration.
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programmable logic architecture.
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remote photoplethy-smography (rPPG).
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https://handle.ncl.edu.tw/11296/cc8x47
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電子資源
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http
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圖書館B1F 博碩士論文專區
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圖書館B1F 博碩士論文專區
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