國立虎尾科技大學 |

Neural Network Reduction for Efficient Execution on Edge Devices.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Neural Network Reduction for Efficient Execution on Edge Devices./
作者:	Mixter, John E.
面頁冊數:	1 online resource (59 pages)
附註:	Source: Dissertations Abstracts International, Volume: 85-07, Section: B.
Contained By:	Dissertations Abstracts International85-07B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9798381374216

Neural Network Reduction for Efficient Execution on Edge Devices.
Mixter, John E.

Neural Network Reduction for Efficient Execution on Edge Devices. - 1 online resource (59 pages)

Source: Dissertations Abstracts International, Volume: 85-07, Section: B.

Thesis (Ph.D.)--The University of Arizona, 2024.

Includes bibliographical references

As the size of neural networks increase, the resources needed to support their execution also increase. This presents a barrier for creating neural networks that can be trained and executed within resource limited embedded systems. To reduce the resources needed to execute neural networks, weight reduction is often the first target. A network that has been significantly pruned can be executed on-chip, that is, in low SWaP hardware. But, this does not enable either training or pruning in embedded hardware which first requires a full-sized network to fit within the restricted resources. We introduce two methods of network reduction that allows neural networks to be grown and trained within edge devices, Artificial Neurogenesis and Synaptic Input Consolidation.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798381374216Subjects--Topical Terms:

596380
Electrical engineering.
Subjects--Index Terms:

Machine learningIndex Terms--Genre/Form:

554714
Electronic books.

Neural Network Reduction for Efficient Execution on Edge Devices.
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