國立虎尾科技大學 |

A Power-Performance Comparison of CMOS Tunable-Delay Clock Buffers.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	A Power-Performance Comparison of CMOS Tunable-Delay Clock Buffers./
作者:	Wu, Jiaqi.
面頁冊數:	1 online resource (71 pages)
附註:	Source: Masters Abstracts International, Volume: 84-09.
Contained By:	Masters Abstracts International84-09.
標題:	Computer engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9798377616559

A Power-Performance Comparison of CMOS Tunable-Delay Clock Buffers.
Wu, Jiaqi.

A Power-Performance Comparison of CMOS Tunable-Delay Clock Buffers. - 1 online resource (71 pages)

Source: Masters Abstracts International, Volume: 84-09.

Thesis (M.A.S.)--University of Toronto (Canada), 2023.

Includes bibliographical references

This thesis presents a systematic comparison of the power-supply induced jitter (PSIJ), random jitter (RJ) generation and random jitter amplification (RJA) of different CMOS tunable-delay clock buffers in GF 45-nm PDSOI technology. Under the proposed comparison methodology, inductive peaking buffer architectures using passive and active inductors were found to have the best jitter performance. Passive inductors require large areas at moderate clock frequencies and thus are impractical for most applications. A novel active inductive peaking buffer architecture is proposed as an alternative, improving upon the state-of-the-art by reducing the self-loading effect and improving jitter attenuation. The clocks of two different digitally-controlled delay lines ( DCDL) using shunt capacitor buffers and the proposed active inductive peaking buffers were used at the final multiplexer stage of a prototype 25 Gb/s NRZ transmitter. The resulting post-layout simulated transmitter output jitter shows a 30% reduction using the proposed active inductive peaking buffer design.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798377616559Subjects--Topical Terms:

569006
Computer engineering.
Subjects--Index Terms:

Clock bufferingIndex Terms--Genre/Form:

554714
Electronic books.

A Power-Performance Comparison of CMOS Tunable-Delay Clock Buffers.
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504 $a Includes bibliographical references
520 $a This thesis presents a systematic comparison of the power-supply induced jitter (PSIJ), random jitter (RJ) generation and random jitter amplification (RJA) of different CMOS tunable-delay clock buffers in GF 45-nm PDSOI technology. Under the proposed comparison methodology, inductive peaking buffer architectures using passive and active inductors were found to have the best jitter performance. Passive inductors require large areas at moderate clock frequencies and thus are impractical for most applications. A novel active inductive peaking buffer architecture is proposed as an alternative, improving upon the state-of-the-art by reducing the self-loading effect and improving jitter attenuation. The clocks of two different digitally-controlled delay lines ( DCDL) using shunt capacitor buffers and the proposed active inductive peaking buffers were used at the final multiplexer stage of a prototype 25 Gb/s NRZ transmitter. The resulting post-layout simulated transmitter output jitter shows a 30% reduction using the proposed active inductive peaking buffer design.
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538 $a Mode of access: World Wide Web
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650 4 $a Electrical engineering. $3 596380
653 $a Clock buffering
653 $a Digitally-controlled delay line
653 $a Power-supply induced jitter
653 $a Random jitter
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