國立虎尾科技大學 |

A Secure SoC Platform for Security Assessments in FPGAs.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	A Secure SoC Platform for Security Assessments in FPGAs./
作者:	Nicholas, Geraldine Shirley.
面頁冊數:	1 online resource (113 pages)
附註:	Source: Dissertations Abstracts International, Volume: 84-11, Section: B.
Contained By:	Dissertations Abstracts International84-11B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9798379453572

A Secure SoC Platform for Security Assessments in FPGAs.
Nicholas, Geraldine Shirley.

A Secure SoC Platform for Security Assessments in FPGAs. - 1 online resource (113 pages)

Source: Dissertations Abstracts International, Volume: 84-11, Section: B.

Thesis (Ph.D.)--The University of North Carolina at Charlotte, 2023.

Includes bibliographical references

With the rapid increase in connected devices and SoC design architecture being used in diverse platforms, they become potential targets to gain unauthorized access for data and privacy invasion. Therefore, heterogeneous SoC architecture raises security concerns in addition to the benefits they offer with improved throughput. They are susceptible to side-channel attacks where secure information is extracted through communication channels. Crypto algorithms implemented for secure authentication tend to leak sensitive information jeopardizing system security. Memory corruption vulnerabilities, code injection, buffer overflow attacks and other software-based attacks through untrusted channels tend to control the flow of the application with malicious data. Though traditional defense mechanisms have been implemented they are all still vulnerable to side-channel attacks.Secure measures to protect the interfaces and data propagation through different channels are critical and building a resilient model consists of the on-chip security factors. In this work, a platform based SoC model is implemented to meet the security objectives using the RISC-V architecture in which an information flow tracking module tracks the flow of data for the system's integrity along with crypto engines and a secure boot mechanism for secure device authentication providing encrypted data transfers. For bitstream resilient SoC models the work extends a logic obfuscation module with runtime security leading to a secure assessment framework. This work explores the microarchitectural vulnerabilities with Machine Learning models and proposes a Transfer Learning technique based counterfeit detection scheme for supply chain vulnerability.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798379453572Subjects--Topical Terms:

596380
Electrical engineering.
Subjects--Index Terms:

SoC designIndex Terms--Genre/Form:

554714
Electronic books.

A Secure SoC Platform for Security Assessments in FPGAs.
LDR:03090ntm a22003977 4500 001 1141727
005 20240414211457.5
006 m o d
007 cr mn ---uuuuu
008 250605s2023 xx obm 000 0 eng d
020 $a 9798379453572
035 $a (MiAaPQ)AAI30424494
035 $a AAI30424494
040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Nicholas, Geraldine Shirley. $3 1465678
245 1 2 $a A Secure SoC Platform for Security Assessments in FPGAs.
264 0 $c 2023
300 $a 1 online resource (113 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertations Abstracts International, Volume: 84-11, Section: B.
500 $a Advisor: Saqib, Fareena.
502 $a Thesis (Ph.D.)--The University of North Carolina at Charlotte, 2023.
504 $a Includes bibliographical references
520 $a With the rapid increase in connected devices and SoC design architecture being used in diverse platforms, they become potential targets to gain unauthorized access for data and privacy invasion. Therefore, heterogeneous SoC architecture raises security concerns in addition to the benefits they offer with improved throughput. They are susceptible to side-channel attacks where secure information is extracted through communication channels. Crypto algorithms implemented for secure authentication tend to leak sensitive information jeopardizing system security. Memory corruption vulnerabilities, code injection, buffer overflow attacks and other software-based attacks through untrusted channels tend to control the flow of the application with malicious data. Though traditional defense mechanisms have been implemented they are all still vulnerable to side-channel attacks.Secure measures to protect the interfaces and data propagation through different channels are critical and building a resilient model consists of the on-chip security factors. In this work, a platform based SoC model is implemented to meet the security objectives using the RISC-V architecture in which an information flow tracking module tracks the flow of data for the system's integrity along with crypto engines and a secure boot mechanism for secure device authentication providing encrypted data transfers. For bitstream resilient SoC models the work extends a logic obfuscation module with runtime security leading to a secure assessment framework. This work explores the microarchitectural vulnerabilities with Machine Learning models and proposes a Transfer Learning technique based counterfeit detection scheme for supply chain vulnerability.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2024
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
650 4 $a Computer engineering. $3 569006
653 $a SoC design
653 $a Data invasion
653 $a Crypto alogorithms
653 $a RISC-V
653 $a Network security
653 $a FPGAs
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
690 $a 0464
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a The University of North Carolina at Charlotte. $b Electrical Engineering. $3 1182889
773 0 $t Dissertations Abstracts International $g 84-11B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=30424494 $z click for full text (PQDT)