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An FPGA Implementation of SipHash.
紀錄類型:
書目-語言資料,手稿 : Monograph/item
正題名/作者:
An FPGA Implementation of SipHash./
作者:
Welte, Benjamin.
面頁冊數:
1 online resource (36 pages)
附註:
Source: Masters Abstracts International, Volume: 84-12.
Contained By:
Masters Abstracts International84-12.
標題:
Information technology. -
電子資源:
click for full text (PQDT)
ISBN:
9798379748227
An FPGA Implementation of SipHash.
Welte, Benjamin.
An FPGA Implementation of SipHash.
- 1 online resource (36 pages)
Source: Masters Abstracts International, Volume: 84-12.
Thesis (M.S.)--Iowa State University, 2023.
Includes bibliographical references
Cryptographic hash functions play a critical role in ensuring the security and veracity of network transactions; for example, they constitute the backbone of hash-based message authentication codes (HMACs), distributed hash tables (DHTs), and blockchain. However, despite cryptographic hashing's security and error-correction capabilities, it can incur significant CPU overhead, especially for applications that commonly process large inputs exceeding 1 MB. This can make it infeasible to implement HMACs, DHTs, etc. in resource-constrained embedded systems or servers with strict response time requirements. As a solution, we present an FPGA architecture to accelerate SipHash, a promising cryptographic hash function. Our design constitutes the first SipHash implementation that targets maximum performance on an FPGA. The proposed architecture's throughput and acceleration vs. software were measured on Xilinx's Zynq-7000 and Ultrascale+ SoCs for a wide range of input sizes. These results show one core can provide single-threaded throughput of up to 13.7 Gbps on a modern FPGA fabric, and multiple parallel cores can nearly reach 100 Gbps, allowing applications like blockchain and peer-to-peer file sharing to scale with emerging high-bandwidth networks. A single core can keep pace with 10 Gigabit Ethernet, and further parallelization can empower FPGA designs to fully utilize higher network bandwidths.
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024
Mode of access: World Wide Web
ISBN: 9798379748227Subjects--Topical Terms:
559429
Information technology.
Subjects--Index Terms:
FPGA acceleratorIndex Terms--Genre/Form:
554714
Electronic books.
An FPGA Implementation of SipHash.
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Cryptographic hash functions play a critical role in ensuring the security and veracity of network transactions; for example, they constitute the backbone of hash-based message authentication codes (HMACs), distributed hash tables (DHTs), and blockchain. However, despite cryptographic hashing's security and error-correction capabilities, it can incur significant CPU overhead, especially for applications that commonly process large inputs exceeding 1 MB. This can make it infeasible to implement HMACs, DHTs, etc. in resource-constrained embedded systems or servers with strict response time requirements. As a solution, we present an FPGA architecture to accelerate SipHash, a promising cryptographic hash function. Our design constitutes the first SipHash implementation that targets maximum performance on an FPGA. The proposed architecture's throughput and acceleration vs. software were measured on Xilinx's Zynq-7000 and Ultrascale+ SoCs for a wide range of input sizes. These results show one core can provide single-threaded throughput of up to 13.7 Gbps on a modern FPGA fabric, and multiple parallel cores can nearly reach 100 Gbps, allowing applications like blockchain and peer-to-peer file sharing to scale with emerging high-bandwidth networks. A single core can keep pace with 10 Gigabit Ethernet, and further parallelization can empower FPGA designs to fully utilize higher network bandwidths.
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