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An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation./
Author:	Raveendran, Srividya.
Description:	1 online resource (73 pages)
Notes:	Source: Masters Abstracts International, Volume: 84-12.
Contained By:	Masters Abstracts International84-12.
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9798379699185

An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation.
Raveendran, Srividya.

An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation. - 1 online resource (73 pages)

Source: Masters Abstracts International, Volume: 84-12.

Thesis (M.S.)--University of Idaho, 2023.

Includes bibliographical references

The Gate All Around (GAA) Field Effect Transistor (FET) is a type of MOS (Metal Oxide Semiconductor) device that circumvents the problem of the existing FinFET devices and produces effective results on scaling up to 7nm technology node and beyond. The significant benefits of this transistor design are size reduction and increased potential for channel length scaling, which attributes to increased transistor density. However, there are some major challenges, like Short Channel Effects (SCE), which include Subthreshold Slope (SS), Drain Induced Barrier lowering (DIBL), and Gate Induced Drain Leakage (GIDL), that are involved in scaling. This paper mainly focuses on reviewing those challenges by analyzing the TCAD simulation results of two different types of GAA FET devices, Nanosheet (NS) and Nanowire (NW), along with the summary of the effect of the width and radius of NS and NW on the above- mentioned short channel effects. A comparative overview of the impact on a single and stacked device is also discussed.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798379699185Subjects--Topical Terms:

596380
Electrical engineering.
Subjects--Index Terms:

Short Channel EffectsIndex Terms--Genre/Form:

554714
Electronic books.

An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation.
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502 $a Thesis (M.S.)--University of Idaho, 2023.
504 $a Includes bibliographical references
520 $a The Gate All Around (GAA) Field Effect Transistor (FET) is a type of MOS (Metal Oxide Semiconductor) device that circumvents the problem of the existing FinFET devices and produces effective results on scaling up to 7nm technology node and beyond. The significant benefits of this transistor design are size reduction and increased potential for channel length scaling, which attributes to increased transistor density. However, there are some major challenges, like Short Channel Effects (SCE), which include Subthreshold Slope (SS), Drain Induced Barrier lowering (DIBL), and Gate Induced Drain Leakage (GIDL), that are involved in scaling. This paper mainly focuses on reviewing those challenges by analyzing the TCAD simulation results of two different types of GAA FET devices, Nanosheet (NS) and Nanowire (NW), along with the summary of the effect of the width and radius of NS and NW on the above- mentioned short channel effects. A comparative overview of the impact on a single and stacked device is also discussed.
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538 $a Mode of access: World Wide Web
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650 4 $a Materials science. $3 557839
650 4 $a Nanoscience. $3 632473
653 $a Short Channel Effects
653 $a FET devices
653 $a Metal Oxide Semiconductor
653 $a Transistor design
653 $a Subthreshold Slope
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