國立虎尾科技大學 |

Demystifying Tail Latency Through Benchmark and Hardware-Software Codesign.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Demystifying Tail Latency Through Benchmark and Hardware-Software Codesign./
作者:	Zhuo, Heng.
面頁冊數:	1 online resource (166 pages)
附註:	Source: Dissertations Abstracts International, Volume: 84-12, Section: B.
Contained By:	Dissertations Abstracts International84-12B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9798379726232

Demystifying Tail Latency Through Benchmark and Hardware-Software Codesign.
Zhuo, Heng.

Demystifying Tail Latency Through Benchmark and Hardware-Software Codesign. - 1 online resource (166 pages)

Source: Dissertations Abstracts International, Volume: 84-12, Section: B.

Thesis (Ph.D.)--The University of Wisconsin - Madison, 2023.

Includes bibliographical references

Server performance has always been an active field of research, spanning topics including databases, network applications, and cloud computing. Tail latency is one of the most important performance metrics for server performance, next to mean latency and throughput. More recently, energy and power consumption also attracts attention for better efficiency. There are many factors that can have an impact on system performance, including software service design and hardware environments.In the first part of this work, we study how different timing components affect server workload performance, including thread contention and interrupt handling. We introduce a workload analysis and generation tool: TailWAG. TailWAG relies on measured timing components from applications to generate a synthetic workload that mimics the original behavior. TailWAG can help server designers and application developers explore performance bottlenecks and optimization opportunities at early stages.Then in the next part, we described how interrupt handling and its interaction with synchronization is one of the root causes of tail latency. In addition, we evaluate a recent feature addition to Linux kernel 5.12: threaded NAPI, which improves classic network interrupt handling with controllable scheduling, reducing the asynchronous penalty from the bottom half of network interrupt handling.Based on the implication from the interaction, we take a further step by proposing a pair of tightly coupled accelerators: one for targeting the top half of the interrupt, and one for managing spin lock timeouts. In combination, these accelerators can prevent cascading timing disturbances for multi-threaded server workloads and save CPU energy consumption.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798379726232Subjects--Topical Terms:

596380
Electrical engineering.
Subjects--Index Terms:

Hardware acceleratorIndex Terms--Genre/Form:

554714
Electronic books.

Demystifying Tail Latency Through Benchmark and Hardware-Software Codesign.
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