國立虎尾科技大學 |

Enhanced-Entropy Chaotic Circuit Design for Overhead-Constrained Hardware Security Applications in Integrated Circuits.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Enhanced-Entropy Chaotic Circuit Design for Overhead-Constrained Hardware Security Applications in Integrated Circuits./
作者:	Paul, Partha Sarathi.
面頁冊數:	1 online resource (195 pages)
附註:	Source: Dissertations Abstracts International, Volume: 85-04, Section: A.
Contained By:	Dissertations Abstracts International85-04A.
標題:	Information science. -
電子資源:	click for full text (PQDT)
ISBN:	9798380579599

Enhanced-Entropy Chaotic Circuit Design for Overhead-Constrained Hardware Security Applications in Integrated Circuits.
Paul, Partha Sarathi.

Enhanced-Entropy Chaotic Circuit Design for Overhead-Constrained Hardware Security Applications in Integrated Circuits. - 1 online resource (195 pages)

Source: Dissertations Abstracts International, Volume: 85-04, Section: A.

Thesis (Ph.D.)--The University of Mississippi, 2023.

Includes bibliographical references

This document presents a Ph.D. dissertation that focuses on designing overhead-constrained circuits for chaos-based hardware security applications in integrated circuit (IC) technology. The designed circuits are optimized for promising chaotic behavior while maintaining the constrained area, delay, and power budget. This research includes proposing novel circuit topologies for attaining superior chaotic complexity, analyzing chaotic performance with multiple metrics, proposing the designs for real-world hardware-security applications that leverage proposed circuit topologies, and analyzing the security aspects of the designed applications. Multiple circuit design techniques are presented in this document. All the proposed works fall under the central motivation of designing low-area, low-power, and high-speed chaos-generating circuits that are suitable for chaos-based hardware security applications in the IC environment. Propositions are discussed with the design motivation, the general framework of the design, design implementation for Cadence-based simulation, evaluation of chaotic performance, and the analysis of circuit overhead cost. Applications of the proposed topologies in the real-world hardware-security protocol are discussed, as well. It is demonstrated that the proposed circuit topologies are suitable to implement chaos-based hardware security protocols for overhead-constrained IC applications.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798380579599Subjects--Topical Terms:

561178
Information science.
Subjects--Index Terms:

Analog chaotic mapsIndex Terms--Genre/Form:

554714
Electronic books.

Enhanced-Entropy Chaotic Circuit Design for Overhead-Constrained Hardware Security Applications in Integrated Circuits.
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