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Deadlock Freedom in Relative-Timed Asynchronous Networks-on-Chip.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Deadlock Freedom in Relative-Timed Asynchronous Networks-on-Chip./
作者:	Nori, Venkata Sai MadhuKiran Harsha.
面頁冊數:	1 online resource (103 pages)
附註:	Source: Dissertations Abstracts International, Volume: 85-04, Section: A.
Contained By:	Dissertations Abstracts International85-04A.
標題:	Computer engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9798380590709

Deadlock Freedom in Relative-Timed Asynchronous Networks-on-Chip.
Nori, Venkata Sai MadhuKiran Harsha.

Deadlock Freedom in Relative-Timed Asynchronous Networks-on-Chip. - 1 online resource (103 pages)

Source: Dissertations Abstracts International, Volume: 85-04, Section: A.

Thesis (Ph.D.)--The University of Utah, 2023.

Includes bibliographical references

Unlike traditional synchronous design, which has a specific modus operandi, Relative Timing (RT) design is flexible. This pliability leads to exciting opportunities in engineering and research. With progression in scaling, it becomes necessary for a designer to consider all possible points of contrariety. Timing is one such point. Differences in timing, either by design or in the device, can be manifested in the circuit as something gratuitous. Making a design conform to the required timing constraints becomes challenging as the circuit and interconnect complexity increases.There have been discussions about deadlock-freedom in interconnection networks. A widely accepted necessary and sufficient condition for this is to show that the processes and resources are acyclic. In a networks-on-chip context, a channel dependency graph captures the dependencies a routing algorithm induces. If this graph is acyclic, then the network is entirely deadlock-free for that algorithm. While universal and still applicable to relative-timed networks, the problem with this approach roots from the mere existence of a wide gamut of routing algorithms and network styles. Every network requires a careful inspection, both in terms of its topology and algorithm, to prove deadlock freedom.This dissertation provides a robust methodology for designing deadlock-free, relative-timed (RT) networks-on-chip (NoC). Multiple relative-timed NoCs are designed, synthesized, and simulated to understand the design's deadlock properties and implications of relative timing constraints. A novel router design is implemented using source asynchronous signaling (SAS) protocol, and the design is evaluated. Furthermore, various approaches to optimize the utilization of SAS for design are investigated.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798380590709Subjects--Topical Terms:

569006
Computer engineering.
Subjects--Index Terms:

Synchronous designIndex Terms--Genre/Form:

554714
Electronic books.

Deadlock Freedom in Relative-Timed Asynchronous Networks-on-Chip.
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