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Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters./
Author:	Biswas, Ayan.
Description:	1 online resource (77 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 85-03, Section: B.
Contained By:	Dissertations Abstracts International85-03B.
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9798380366946

Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters.
Biswas, Ayan.

Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters. - 1 online resource (77 pages)

Source: Dissertations Abstracts International, Volume: 85-03, Section: B.

Thesis (Ph.D.)--University of California, Berkeley, 2023.

Includes bibliographical references

With the ever increasing bandwidth demand in high performance computing, network and communications, machine learning applications, etc, wireline data transfer between multiple chips on the same package has been doubling in per-lane data rate every 3-4 years. The challenging design complexity of the analog and mixed signal front-end circuits necessitates the use of automated process portable layout generators and closed loop design scripts to reduce the turn-around time from circuit design to tape-outs in advanced FinFET technology nodes.To that end, this thesis introduces new feature improvements in the Berkeley Analog Generator (BAG) 3++, which is an open source framework for automating process portable circuit generation and encoding closed loop design methodologies. Then the thesis presents the design of a 160 Gbps NRZ transmitter (TX) targeting low loss (∼3dB) ultra short reach channels for die-to-die data transfer, with 2 tap FFE for pre-equalization. Some major challenges in this effort are the design of a high speed 8:1 mux stage using inductor-based peaking topologies, and a novel method of creating the 1 UI delayed data stream for the FFE precursor using the available octature clock phases. The TX is taped out in Intel16 process as a part of a complete 160 Gbps NRZ transceiver design, and tested in loopback mode by serially transmitting data to the receiver over a 8.5 mm differential channel on package.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798380366946Subjects--Topical Terms:

596380
Electrical engineering.
Subjects--Index Terms:

Analog and mixed signalIndex Terms--Genre/Form:

554714
Electronic books.

Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters.
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502 $a Thesis (Ph.D.)--University of California, Berkeley, 2023.
504 $a Includes bibliographical references
520 $a With the ever increasing bandwidth demand in high performance computing, network and communications, machine learning applications, etc, wireline data transfer between multiple chips on the same package has been doubling in per-lane data rate every 3-4 years. The challenging design complexity of the analog and mixed signal front-end circuits necessitates the use of automated process portable layout generators and closed loop design scripts to reduce the turn-around time from circuit design to tape-outs in advanced FinFET technology nodes.To that end, this thesis introduces new feature improvements in the Berkeley Analog Generator (BAG) 3++, which is an open source framework for automating process portable circuit generation and encoding closed loop design methodologies. Then the thesis presents the design of a 160 Gbps NRZ transmitter (TX) targeting low loss (∼3dB) ultra short reach channels for die-to-die data transfer, with 2 tap FFE for pre-equalization. Some major challenges in this effort are the design of a high speed 8:1 mux stage using inductor-based peaking topologies, and a novel method of creating the 1 UI delayed data stream for the FFE precursor using the available octature clock phases. The TX is taped out in Intel16 process as a part of a complete 160 Gbps NRZ transceiver design, and tested in loopback mode by serially transmitting data to the receiver over a 8.5 mm differential channel on package.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2024
538 $a Mode of access: World Wide Web
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650 4 $a Engineering. $3 561152
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653 $a Analog and mixed signal
653 $a Machine learning
653 $a Berkeley Analog Generator
653 $a Closed loop
653 $a Wireline communications
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710 2 $a University of California, Berkeley. $b Electrical Engineering & Computer Sciences. $3 845564
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