國立虎尾科技大學 |

Multi-layer general area gridless detailed routing.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Multi-layer general area gridless detailed routing./
作者:	Fang, Jie.
面頁冊數:	1 online resource (179 pages)
附註:	Source: Dissertations Abstracts International, Volume: 62-11, Section: B.
Contained By:	Dissertations Abstracts International62-11B.
標題:	Computer science. -
電子資源:	click for full text (PQDT)
ISBN:	9780493074368

Multi-layer general area gridless detailed routing.
Fang, Jie.

Multi-layer general area gridless detailed routing. - 1 online resource (179 pages)

Source: Dissertations Abstracts International, Volume: 62-11, Section: B.

Thesis (Ph.D.)--University of California, Los Angeles, 2001.

Includes bibliographical references

Automatic routing is one of the oldest and most fundamental problems in computer-aided design of integrated circuits (IC). It has been studied extensively for over thirty years. However, recent advances in processing technology and design methodology have brought new challenges to the routing automation problem. As the VLSI technology reaches deep sub-micro devices and gigahertz clock frequencies, interconnect has become the dominating factor in determining the performance, power and reliability of the circuit. Various optimization algorithms are needed to handle the delay, power and noise problems. These algorithms impose variable width and variable spacing design rule requirements on the routing algorithm. Moreover, the complexity of IC design problem has increased significantly with the shrinking of the transistor feature size. This imposes a serious scaling problem for the full-chip level routing. These advancements in the IC technology brings several challenges to the detailed routing problem as well as the overall routing systems. First, an efficient multi-layer gridless routing engine is needed to route the interconnects with variable width and variable spacing constraints. Second, a highly scalable and flexible routing system is needed to integrate various optimization algorithms and the gridless detailed routing algorithms to handle the routing problem. In this dissertation, we present a multi-layer general-area detailed routing system. It features an efficient gridless point-to-point detailed routing algorithm as the routing engine. An implicit representation of a non-uniform grid graph is proposed as the underlying routing graph and a path-based maze searching engine is developed to search for the paths on the graph. Our gridless detailed routing system also features a unique wire planning algorithm. The planning algorithm not only guides our gridless detailed routing engine but also provides ripup and re-routing capabilities for the detailed routing system. Lastly, we propose a routing system featuring a multilevel framework. The proposed framework is highly scalable to large routing problems and flexible in integrating various optimization algorithms into the routing system. The proposed routing system can be used for high performance IC, multi-chip module (MCM), or printed circuit board (PCB) designs. It can also be used in full custom IC layout, as for the cell library design and the analog circuit design.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9780493074368Subjects--Topical Terms:

573171
Computer science.
Subjects--Index Terms:

GridlessIndex Terms--Genre/Form:

554714
Electronic books.

Multi-layer general area gridless detailed routing.
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504 $a Includes bibliographical references
520 $a Automatic routing is one of the oldest and most fundamental problems in computer-aided design of integrated circuits (IC). It has been studied extensively for over thirty years. However, recent advances in processing technology and design methodology have brought new challenges to the routing automation problem. As the VLSI technology reaches deep sub-micro devices and gigahertz clock frequencies, interconnect has become the dominating factor in determining the performance, power and reliability of the circuit. Various optimization algorithms are needed to handle the delay, power and noise problems. These algorithms impose variable width and variable spacing design rule requirements on the routing algorithm. Moreover, the complexity of IC design problem has increased significantly with the shrinking of the transistor feature size. This imposes a serious scaling problem for the full-chip level routing. These advancements in the IC technology brings several challenges to the detailed routing problem as well as the overall routing systems. First, an efficient multi-layer gridless routing engine is needed to route the interconnects with variable width and variable spacing constraints. Second, a highly scalable and flexible routing system is needed to integrate various optimization algorithms and the gridless detailed routing algorithms to handle the routing problem. In this dissertation, we present a multi-layer general-area detailed routing system. It features an efficient gridless point-to-point detailed routing algorithm as the routing engine. An implicit representation of a non-uniform grid graph is proposed as the underlying routing graph and a path-based maze searching engine is developed to search for the paths on the graph. Our gridless detailed routing system also features a unique wire planning algorithm. The planning algorithm not only guides our gridless detailed routing engine but also provides ripup and re-routing capabilities for the detailed routing system. Lastly, we propose a routing system featuring a multilevel framework. The proposed framework is highly scalable to large routing problems and flexible in integrating various optimization algorithms into the routing system. The proposed routing system can be used for high performance IC, multi-chip module (MCM), or printed circuit board (PCB) designs. It can also be used in full custom IC layout, as for the cell library design and the analog circuit design.
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