國立虎尾科技大學 |

Developing, Synthesizing, and Automating Domain-Specific Accelerators.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Developing, Synthesizing, and Automating Domain-Specific Accelerators./
作者:	Weng, Jian.
面頁冊數:	1 online resource (219 pages)
附註:	Source: Dissertations Abstracts International, Volume: 85-03, Section: B.
Contained By:	Dissertations Abstracts International85-03B.
標題:	Computer engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9798380336918

Developing, Synthesizing, and Automating Domain-Specific Accelerators.
Weng, Jian.

Developing, Synthesizing, and Automating Domain-Specific Accelerators. - 1 online resource (219 pages)

Source: Dissertations Abstracts International, Volume: 85-03, Section: B.

Thesis (Ph.D.)--University of California, Los Angeles, 2023.

Includes bibliographical references

The once exponential general purpose processors' (e.g. CPUs) growth of speedup driven by transistor scaling is fading, which urges both industry and academia to find more energy-efficient and performant architecture organization. Therefore, research on accelerators specialized for applications of interest emerges because of their promising speedup and energy saving while retaining flexibility. To design and implement specialized accelerators, intensive human effort is required to study the target applications and determine tradeoffs between performance and cost. In addition, these newly proposed hardware often implies lagging compilation techniques, which hinders the programming productivity. All these facts significantly limits the programmable accelerator adoption.Moreover, all the prior development effort can hardly be reused in other applicable domains, because the current software/hardware co-designed innovations seldom consider modularity for future integration. Therefore, research projects presented in this dissertation aim at significantly reforming the full-stack reconfigurable accelerator design paradigm: Ideally, each software/hardware co-design feature can be comprised in a universal design space for further accelerator composition so that people no longer build accelerators from scratch. Further, an accelerator can be automatically generated based on the given applications of interest written in a unified high-level programming interface.To achieve this goal, this dissertation develops the framework, DSAGEN, including an accelerator design space with rich software/hardware co-design features, a compiler targets to accelerators with arbitrary design points within this space, and a design automation algorithm that efficiently searches this space. According to our evaluation, the compiler can robustly target multiple application suites on hardware with arbitrary feature combinations. The framework-generated accelerators can have comparable perf/mm2 compared with prior handcrafted domain-specific accelerators.In addition, to demonstrate the wide applicability of our approach, the insights and principles learned along with this goal are also applied to applicable research questions: By deploying the DSAGEN-generated accelerator as a reconfigurable overlay on FPGA, it saves orders-of-magnitude time on compilation and reconfiguration compared with conventional high-level synthesis, while retaining flexibility. This approach suggests that a deeply specialized programmable overlay accelerator can potentially supplement the existing FPGA's high-level programming paradigm. Also, the compilation techniques for spatial architectures developed in DSAGEN can be applied to compiling an emerging instruction paradigm specialized for tensor operations - a productive and extensible compilation framework, UNIT, is presented for these instructions. The extensibility of this framework allows developers to easily integrate new instructions by describing the instruction semantics. High-performance code, that outperforms vendor provided libraries up to 2.2x, for end-to-end inferences can be generated by tensorized rewriting, accompanied with our automated tuning strategies.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798380336918Subjects--Topical Terms:

569006
Computer engineering.
Subjects--Index Terms:

CompilerIndex Terms--Genre/Form:

554714
Electronic books.

Developing, Synthesizing, and Automating Domain-Specific Accelerators.
LDR:04585ntm a22003857 4500 001 1149070
005 20240930130040.5
006 m o d
007 cr bn ---uuuuu
008 250605s2023 xx obm 000 0 eng d
020 $a 9798380336918
035 $a (MiAaPQ)AAI30638450
035 $a AAI30638450
040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Weng, Jian. $3 787769
245 1 0 $a Developing, Synthesizing, and Automating Domain-Specific Accelerators.
264 0 $c 2023
300 $a 1 online resource (219 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertations Abstracts International, Volume: 85-03, Section: B.
500 $a Advisor: Nowatzki, Anthony John.
502 $a Thesis (Ph.D.)--University of California, Los Angeles, 2023.
504 $a Includes bibliographical references
520 $a The once exponential general purpose processors' (e.g. CPUs) growth of speedup driven by transistor scaling is fading, which urges both industry and academia to find more energy-efficient and performant architecture organization. Therefore, research on accelerators specialized for applications of interest emerges because of their promising speedup and energy saving while retaining flexibility. To design and implement specialized accelerators, intensive human effort is required to study the target applications and determine tradeoffs between performance and cost. In addition, these newly proposed hardware often implies lagging compilation techniques, which hinders the programming productivity. All these facts significantly limits the programmable accelerator adoption.Moreover, all the prior development effort can hardly be reused in other applicable domains, because the current software/hardware co-designed innovations seldom consider modularity for future integration. Therefore, research projects presented in this dissertation aim at significantly reforming the full-stack reconfigurable accelerator design paradigm: Ideally, each software/hardware co-design feature can be comprised in a universal design space for further accelerator composition so that people no longer build accelerators from scratch. Further, an accelerator can be automatically generated based on the given applications of interest written in a unified high-level programming interface.To achieve this goal, this dissertation develops the framework, DSAGEN, including an accelerator design space with rich software/hardware co-design features, a compiler targets to accelerators with arbitrary design points within this space, and a design automation algorithm that efficiently searches this space. According to our evaluation, the compiler can robustly target multiple application suites on hardware with arbitrary feature combinations. The framework-generated accelerators can have comparable perf/mm2 compared with prior handcrafted domain-specific accelerators.In addition, to demonstrate the wide applicability of our approach, the insights and principles learned along with this goal are also applied to applicable research questions: By deploying the DSAGEN-generated accelerator as a reconfigurable overlay on FPGA, it saves orders-of-magnitude time on compilation and reconfiguration compared with conventional high-level synthesis, while retaining flexibility. This approach suggests that a deeply specialized programmable overlay accelerator can potentially supplement the existing FPGA's high-level programming paradigm. Also, the compilation techniques for spatial architectures developed in DSAGEN can be applied to compiling an emerging instruction paradigm specialized for tensor operations - a productive and extensible compilation framework, UNIT, is presented for these instructions. The extensibility of this framework allows developers to easily integrate new instructions by describing the instruction semantics. High-performance code, that outperforms vendor provided libraries up to 2.2x, for end-to-end inferences can be generated by tensorized rewriting, accompanied with our automated tuning strategies.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2024
538 $a Mode of access: World Wide Web
650 4 $a Computer engineering. $3 569006
650 4 $a Computer science. $3 573171
653 $a Compiler
653 $a Computer architecture
653 $a Design automation
653 $a Full-stack
653 $a Tensorized rewriting
655 7 $a Electronic books. $2 local $3 554714
690 $a 0984
690 $a 0464
710 2 $a University of California, Los Angeles. $b Computer Science 0201. $3 1182286
710 2 $a ProQuest Information and Learning Co. $3 1178819
773 0 $t Dissertations Abstracts International $g 85-03B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=30638450 $z click for full text (PQDT)