國立虎尾科技大學 |

Nanoscale Device Design : = A TCAD Analysis of 2nm GAAFET Nanosheet.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Nanoscale Device Design :/
Reminder of title:	A TCAD Analysis of 2nm GAAFET Nanosheet.
Author:	Totorica, Nathan.
Description:	1 online resource (43 pages)
Notes:	Source: Masters Abstracts International, Volume: 85-11.
Contained By:	Masters Abstracts International85-11.
Subject:	Engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9798382732558

Nanoscale Device Design : = A TCAD Analysis of 2nm GAAFET Nanosheet.
Totorica, Nathan.

Nanoscale Device Design :A TCAD Analysis of 2nm GAAFET Nanosheet. - 1 online resource (43 pages)

Source: Masters Abstracts International, Volume: 85-11.

Thesis (M.S.)--University of Idaho, 2024.

Includes bibliographical references

The size of field effect transistors used in CMOS integrated circuits shrinks over each technology node to achieve lower power consumption, higher performance, and higher density. The increase in electrostatic control and reduced short channel effects (SCE) are key benefits to adopting new architectures like Gate-All-Around FET (GAAFET) to meet scaling requirements for next generation process nodes. Advanced architectures in the nanometer regime bring unique design challenges that require thorough characterization of device performance to ensure a successful and robust implementation. Sentaurus TCAD provides a valuable tool to begin exploring the many design choices faced when encountering a novel structure such as GAAFET. Design choices around device geometries and materials can be simulated to understand impacts on performance. In this work, several of these design choices are explored, such as channel geometry, vertical channel stacking, and spacer material options, all while using the projected parameters of the 2nm node. Key device metrics like transfer characteristics, SCE, extension resistance, and gate capacitances are used to create a basis for evaluating the design health. The devices designed using TCAD are then simulated at the circuit level to further explore tradeoffs and provide additional figure of merits into device performance.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798382732558Subjects--Topical Terms:

561152
Engineering.
Subjects--Index Terms:

Gate-All-Around FETIndex Terms--Genre/Form:

554714
Electronic books.

Nanoscale Device Design : = A TCAD Analysis of 2nm GAAFET Nanosheet.
LDR:02690ntm a22003977 4500 001 1149860
005 20241022110534.5
006 m o d
007 cr bn ---uuuuu
008 250605s2024 xx obm 000 0 eng d
020 $a 9798382732558
035 $a (MiAaPQ)AAI31238349
035 $a AAI31238349
040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Totorica, Nathan. $3 1476228
245 1 0 $a Nanoscale Device Design : $b A TCAD Analysis of 2nm GAAFET Nanosheet.
264 0 $c 2024
300 $a 1 online resource (43 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 85-11.
500 $a Advisor: Li, Feng.
502 $a Thesis (M.S.)--University of Idaho, 2024.
504 $a Includes bibliographical references
520 $a The size of field effect transistors used in CMOS integrated circuits shrinks over each technology node to achieve lower power consumption, higher performance, and higher density. The increase in electrostatic control and reduced short channel effects (SCE) are key benefits to adopting new architectures like Gate-All-Around FET (GAAFET) to meet scaling requirements for next generation process nodes. Advanced architectures in the nanometer regime bring unique design challenges that require thorough characterization of device performance to ensure a successful and robust implementation. Sentaurus TCAD provides a valuable tool to begin exploring the many design choices faced when encountering a novel structure such as GAAFET. Design choices around device geometries and materials can be simulated to understand impacts on performance. In this work, several of these design choices are explored, such as channel geometry, vertical channel stacking, and spacer material options, all while using the projected parameters of the 2nm node. Key device metrics like transfer characteristics, SCE, extension resistance, and gate capacitances are used to create a basis for evaluating the design health. The devices designed using TCAD are then simulated at the circuit level to further explore tradeoffs and provide additional figure of merits into device performance.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2024
538 $a Mode of access: World Wide Web
650 4 $a Engineering. $3 561152
650 4 $a Nanoscience. $3 632473
650 4 $a Applied physics. $3 1181953
650 4 $a Electrical engineering. $3 596380
653 $a Gate-All-Around FET
653 $a Short channel effects
653 $a Electrostatics
653 $a Spacer materials
655 7 $a Electronic books. $2 local $3 554714
690 $a 0537
690 $a 0565
690 $a 0544
690 $a 0215
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Idaho. $b Electrical and Computer Engineering. $3 1213889
773 0 $t Masters Abstracts International $g 85-11.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31238349 $z click for full text (PQDT)