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Implementation of Shadow Stack Security Design in RISC-V Architecture /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Implementation of Shadow Stack Security Design in RISC-V Architecture // Chiachen Terry Yuan.
作者:	Yuan, Chiachen Terry,
面頁冊數:	1 electronic resource (108 pages)
附註:	Source: Masters Abstracts International, Volume: 86-07.
Contained By:	Masters Abstracts International86-07.
標題:	Computer engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31294791
ISBN:	9798302159359

Implementation of Shadow Stack Security Design in RISC-V Architecture /
Yuan, Chiachen Terry,

Implementation of Shadow Stack Security Design in RISC-V Architecture /Chiachen Terry Yuan. - 1 electronic resource (108 pages)

Source: Masters Abstracts International, Volume: 86-07.

In light of constantly resurfacing and new attack vectors, engineers and researchers have opted for both software and hardware-based defense mechanisms. The RISC-V ISA, introduced in 2014, is a new, open-source, universal standard that has multiple papers and reports made utilizing it to develop hardware-based security solutions. This work targets the implementation of a shadow stack to provide protection on a per-stack frame basis, forcing data passing between two frames needing encryption and checking mechanisms to properly perform what is expected. The implementation, called Shadow Stack Concept (SSC), is a single key generation and storage module implemented onto the Rocket Core processor implementation of the RISC-V ISA. The design is intended to be lightweight and easy to implement, with minimal overhead following other shadow stack designs and similar defenses that incorporate in-pipeline encryption.

English

ISBN: 9798302159359Subjects--Topical Terms:

569006
Computer engineering.
Subjects--Index Terms:

Pipeline encryption

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653 $a Attack vectors
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