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Formal Verification Techniques for Microprocessor Security /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Formal Verification Techniques for Microprocessor Security // Nimish Mathure.
作者:	Mathure, Nimish,
面頁冊數:	1 electronic resource (120 pages)
附註:	Source: Dissertations Abstracts International, Volume: 86-03, Section: B.
Contained By:	Dissertations Abstracts International86-03B.
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31329397
ISBN:	9798384103424

Formal Verification Techniques for Microprocessor Security /
Mathure, Nimish,

Formal Verification Techniques for Microprocessor Security /Nimish Mathure. - 1 electronic resource (120 pages)

Source: Dissertations Abstracts International, Volume: 86-03, Section: B.

Microprocessor security is a pressing concern in our rapidly evolving digital systems, where vulnerabilities can lead to a catastrophic consequences. Recent transient execution attack such as Spectre and Micro-architectural data sampling attack such as Rouge In-flight Data Load have demonstrated the urgent need for robust defenses. These attacks exploits the vulnerabilities of the microprocessor caused due to speculative execution, posing significant risks to sensitive data. Consequently several security mitigation methods are proposed in addressing the novel threats. However, the security measures can fall short on addressing the threats, can be infected with hardware Trojans or can be susceptible to bugs in implementation. Formal verification emerges as a potent tool in this context. Formal verification employs mathematical models and propositional logic to rigorously assess microprocessor design's correctness and security properties. In context of security attacks, formal verification can be employed to assess the robustness of the security measures as well as identify any vulnerabilities before they can be exploited. This dissertation encompasses security mitigation methodologies against such attacks as well as the vital connection between microprocessor security and formal verification. Firstly addressed is the intricate challenge of designing and detecting hardware Trojans within a in-ordered pipelined microprocessor circuit. Secondly, the dissertation explores the security attacks with specific focus on Spectre and Rogue In-flight Data Load, the security measures against them, as well as formal verification methodologies tailored for identifying microprocessor architecture design's vulnerability towards the attacks. Also detecting vulnerabilities in microprocessors which employ security measures, caused due to inadequacies in implementation, trojans or bugs. The methodologies proposed within this work demonstrated a detection rate of 100% over several benchmarks, highlighting the effectiveness and reliability.

English

ISBN: 9798384103424Subjects--Topical Terms:

596380
Electrical engineering.
Subjects--Index Terms:

Formal verification

Formal Verification Techniques for Microprocessor Security /
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