語系:
繁體中文
English
說明(常見問題)
登入
回首頁
切換:
標籤
|
MARC模式
|
ISBD
Integrated circuit design = tape-out process with open-source tools /
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Integrated circuit design/ by Susana Ortega Cisneros, Emilio Isaac Baungarten Leon, Pedro Mejia Alvarez.
其他題名:
tape-out process with open-source tools /
作者:
Ortega Cisneros, Susana.
其他作者:
Mejia Alvarez, Pedro.
出版者:
Cham :Springer Nature Switzerland : : 2025.,
面頁冊數:
xi, 111 p. :ill., digital ; : 24 cm.;
Contained By:
Springer Nature eBook
標題:
Open Source. -
電子資源:
https://doi.org/10.1007/978-3-031-92108-7
ISBN:
9783031921087
Integrated circuit design = tape-out process with open-source tools /
Ortega Cisneros, Susana.
Integrated circuit design
tape-out process with open-source tools /[electronic resource] :by Susana Ortega Cisneros, Emilio Isaac Baungarten Leon, Pedro Mejia Alvarez. - Cham :Springer Nature Switzerland :2025. - xi, 111 p. :ill., digital ;24 cm. - SpringerBriefs in computer science,2191-5776. - SpringerBriefs in computer science..
1: Introduction -- 2: Physical Design Flow -- 3: Process Design Kit -- 4: Introduction to OpenLane -- 5: Macro-Cells and RAM-Cells with OpenLane -- 6: Exploring OpenLane through Case Studies and Exercises -- 7: Caravel.
This book provides a structured and comprehensive pathway through the complexities of Electronic Design Automation (EDA) tools and processes. It focuses on OpenLane and Caravel EDA tools, due to their current major role in the open-source IC design ecosystem. OpenLane provides a robust and flexible platform that automates the entire digital design flow from Register Transfer Level (RTL) to Graphic Data System II (GDSII), making it an ideal tool for teaching and learning the physical design process. Caravel, on the other hand, serves as an open-source System on a Chip (SoC) platform, allowing designers to integrate and test their designs in a versatile, real-world environment. It complements OpenLane by enabling users to package and validate their designs, bridging the gap between theoretical knowledge and practical implementation. Together, these tools provide a way to understand the full tape-out process in a way that is accessible to students, researchers, and professionals alike.
ISBN: 9783031921087
Standard No.: 10.1007/978-3-031-92108-7doiSubjects--Topical Terms:
1113081
Open Source.
LC Class. No.: TK7874
Dewey Class. No.: 621.3815
Integrated circuit design = tape-out process with open-source tools /
LDR
:02311nam a2200337 a 4500
001
1161829
003
DE-He213
005
20250513130311.0
006
m d
007
cr nn 008maaau
008
251029s2025 sz s 0 eng d
020
$a
9783031921087
$q
(electronic bk.)
020
$a
9783031921070
$q
(paper)
024
7
$a
10.1007/978-3-031-92108-7
$2
doi
035
$a
978-3-031-92108-7
040
$a
GP
$c
GP
041
0
$a
eng
050
4
$a
TK7874
072
7
$a
UYF
$2
bicssc
072
7
$a
COM011000
$2
bisacsh
072
7
$a
UYF
$2
thema
082
0 4
$a
621.3815
$2
23
090
$a
TK7874
$b
.O7 2025
100
1
$a
Ortega Cisneros, Susana.
$e
author.
$3
1397035
245
1 0
$a
Integrated circuit design
$h
[electronic resource] :
$b
tape-out process with open-source tools /
$c
by Susana Ortega Cisneros, Emilio Isaac Baungarten Leon, Pedro Mejia Alvarez.
260
$a
Cham :
$c
2025.
$b
Springer Nature Switzerland :
$b
Imprint: Springer,
300
$a
xi, 111 p. :
$b
ill., digital ;
$c
24 cm.
490
1
$a
SpringerBriefs in computer science,
$x
2191-5776
505
0
$a
1: Introduction -- 2: Physical Design Flow -- 3: Process Design Kit -- 4: Introduction to OpenLane -- 5: Macro-Cells and RAM-Cells with OpenLane -- 6: Exploring OpenLane through Case Studies and Exercises -- 7: Caravel.
520
$a
This book provides a structured and comprehensive pathway through the complexities of Electronic Design Automation (EDA) tools and processes. It focuses on OpenLane and Caravel EDA tools, due to their current major role in the open-source IC design ecosystem. OpenLane provides a robust and flexible platform that automates the entire digital design flow from Register Transfer Level (RTL) to Graphic Data System II (GDSII), making it an ideal tool for teaching and learning the physical design process. Caravel, on the other hand, serves as an open-source System on a Chip (SoC) platform, allowing designers to integrate and test their designs in a versatile, real-world environment. It complements OpenLane by enabling users to package and validate their designs, bridging the gap between theoretical knowledge and practical implementation. Together, these tools provide a way to understand the full tape-out process in a way that is accessible to students, researchers, and professionals alike.
650
2 4
$a
Open Source.
$3
1113081
650
2 4
$a
Electronic Circuits and Systems.
$3
1366689
650
1 4
$a
Processor Architectures.
$3
669787
650
0
$a
Integrated circuits
$x
Design and construction.
$3
561265
700
1
$a
Mejia Alvarez, Pedro.
$e
author.
$3
1397033
700
1
$a
Baungarten Leon, Emilio Isaac.
$3
1488766
710
2
$a
SpringerLink (Online service)
$3
593884
773
0
$t
Springer Nature eBook
830
0
$a
SpringerBriefs in computer science.
$3
883114
856
4 0
$u
https://doi.org/10.1007/978-3-031-92108-7
950
$a
Computer Science (SpringerNature-11645)
筆 0 讀者評論
多媒體
評論
新增評論
分享你的心得
Export
取書館別
處理中
...
變更密碼[密碼必須為2種組合(英文和數字)及長度為10碼以上]
登入