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Design of a Robust IEEE Compliant Floating-Point Divide and Square Root Using Iterative Approximation

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Design of a Robust IEEE Compliant Floating-Point Divide and Square Root Using Iterative Approximation/ Carson Sager.
作者:	Sager, Carson,
面頁冊數:	1 electronic resource (40 pages)
附註:	Source: Masters Abstracts International, Volume: 87-02.
Contained By:	Masters Abstracts International87-02.
標題:	Computer engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31940703
ISBN:	9798291551967

Design of a Robust IEEE Compliant Floating-Point Divide and Square Root Using Iterative Approximation
Sager, Carson,

Design of a Robust IEEE Compliant Floating-Point Divide and Square Root Using Iterative Approximation [electronic resource] /Carson Sager. - 1 electronic resource (40 pages)

Source: Masters Abstracts International, Volume: 87-02.

In this work, an IEEE 754 compliant normalized floating-point divide and square root unit is presented that utilizes iterative approximation. This research provides a robust architecture that allows multiple formats and all IEEE 754 rounding modes while still exhibiting high-performance. Moreover, this thesis presents a design that adheres to the IEEE 754 2019 standard as well as demonstrating methods for rounding results to all five rounding modes using iterative approximation. Performance, Power, and Area estimates are determined from physical synthesis using ARM-based standard cells in a TSMC 28nm process. This thesis also presents comparisons with other implementations and demonstrates the efficiency of the approach presented here.

English

ISBN: 9798291551967Subjects--Topical Terms:

569006
Computer engineering.
Subjects--Index Terms:

Computer arithmetic

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653 # # $a Iterative approximation
653 # # $a System on chip design
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