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Logic synthesis and verification alg...

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Somenzi, Fabio

Logic synthesis and verification algorithms

Record Type:	Language materials, printed : monographic
Author:	HachtelGary D,
Secondary Intellectual Responsibility:	SomenziFabio,
Place of Publication:	Boston
Published:	Kluwer Academic Publishers;
Year of Publication:	c1996
Description:	xxxi, 564 pill : 26 cm;
Subject:	Integrated circuits - Very large scale integration -
Subject:	Logic design - Data processing -
Subject:	Integrated circuits - Verification -
Subject:	Computer-aided design -
ISBN:	0792397460

Logic synthesis and verification algorithms
Hachtel, Gary D

Logic synthesis and verification algorithms / by Gary D. Hachtel, Fabio Somenzi - Boston : Kluwer Academic Publishers, c1996. - xxxi, 564 p ; ill ; 26 cm.
Includes bibliographical references (p. 537-553) and index.
ISBN 0792397460
Integrated circuitsLogic designIntegrated circuitsComputer-aided design -- Very large scale integration -- Data processing -- Verification

Somenzi, Fabio

Logic synthesis and verification algorithms
LDR:00698cam 2200217 i 450 001 436211
005 20101023212213.0
009 a96021769
010 1 $a 0792397460 $b (hard)
100 $a 20080130d1996 m y0engy01 b
101 0 $a eng
200 1 $a Logic synthesis and verification algorithms $f by Gary D. Hachtel, Fabio Somenzi
210 $a Boston $c Kluwer Academic Publishers $d c1996
215 0 $a xxxi, 564 p $c ill $d 26 cm
320 $a Includes bibliographical references (p. 537-553) and index
606 $a Integrated circuits $x Very large scale integration $3 392457 $2 lc $3 725736
606 $a Logic design $x Data processing $3 414210 $2 lc $3 731607
606 $a Integrated circuits $x Verification $3 415047 $2 lc $3 731608
606 $a Computer-aided design $3 401423 $2 lc $3 724064
676 $a 621.39/5 $v 20
676 $a 621.395 $b H117
680 $a TK7874.75 $b H33 1996
700 $a Hachtel $b Gary D $3 415045
702 $a Somenzi $b Fabio $3 415046
801 0 $b DLC
801 0 $a cw $b BIB $c 19980706
801 1 $a cw $b national library $c 19980706
801 1 $a cw $b 國立國立虎尾科技大學圖書館 $c 19980729 $g CCR

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621.395 H117 1996

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