國立虎尾科技大學 |

登入

回首頁

Integrated Circuit and System Design...

Verkest, Diederik.

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : = 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :/ edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest.
其他題名:	15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
其他題名:	PATMOS 2005
其他作者:	Paliouras, Vassilis.
團體作者:	PATMOS 2005
出版者:	Berlin Heidelberg :Springer-Verlag GmbH., : 2005.,
面頁冊數:	xv, 753 p. :ill., digital ; : 24 cm.;
叢書名:	Lecture Notes in Computer Science,
Contained By:	Springer e-books
標題:	Integrated circuits - Congresses. - Very large scale integration -
電子資源:	http://dx.doi.org/10.1007/11556930
ISBN:	9783540320807 (electronic bk.)

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : = 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings[electronic resource] /PATMOS 2005edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest. - Berlin Heidelberg :Springer-Verlag GmbH.,2005. - xv, 753 p. :ill., digital ;24 cm. - Lecture Notes in Computer Science,37280302-9743 ;.

ISBN: 9783540320807 (electronic bk.)Subjects--Topical Terms:

675648
Integrated circuits
--Very large scale integration--Congresses.

LC Class. No.: TK7874.75 / .P38 2005

Dewey Class. No.: 621.3815

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : = 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
LDR:01045nam a22002535a 4500 001 624854
003 Springer
005 20080501093300.0
006 m d
007 cr nn 008maaau
008 070919s2005 gw j eng d
020 $a 9783540320807 (electronic bk.)
020 $a 9783540290131 (paper)
035 $a 978-3-540-29013-1
050 0 0 $a TK7874.75 $b .P38 2005
082 0 0 $a 621.3815 $2 22
090 $a TK7874.75 $b .P311 2005
111 2 $a PATMOS 2005 $d (2005 : $c Louvain, Belgium) $3 675647
245 1 0 $a Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : $b 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings $h [electronic resource] / $c edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest.
246 3 0 $a PATMOS 2005
260 $a Berlin Heidelberg : $c 2005. $b Springer-Verlag GmbH.,
300 $a xv, 753 p. : $b ill., digital ; $c 24 cm.
440 0 $a Lecture Notes in Computer Science, $x 0302-9743 ; $v 3728
650 0 $a Integrated circuits $x Very large scale integration $x Computer-aided design $v Congresses. $3 675648
650 1 4 $a Computer Science. $3 593922
650 2 4 $a Arithmetic and Logic Structures. $3 672631
650 2 4 $a Computer-Aided Engineering (CAD, CAE) and Design. $3 669928
650 2 4 $a Electronic and Computer Engineering. $3 669852
650 2 4 $a Logic Design. $3 670915
650 2 4 $a Performance and Reliability. $3 669802
650 2 4 $a Processor Architectures. $3 669787
700 1 $a Paliouras, Vassilis. $3 675649
700 1 $a Verkest, Diederik. $3 675650
700 1 $a Vounckx, Johan. $3 675651
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer e-books
856 4 0 $u http://dx.doi.org/10.1007/11556930
950 $a Computer Science (Springer-11645; ZDB-2-SCS)

筆 0 讀者評論

多媒體

評論

新增評論分享你的心得

Export

取書館別