國立虎尾科技大學 |

Language: English

Login

Back

Switch To: Labeled | MARC Mode | ISBD

Writing testbenches using System Ver...

~

Bergeron, Janick.

Writing testbenches using System Verilog /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Writing testbenches using System Verilog // by Janick Bergeron.
Author:	Bergeron, Janick.
other author:	Bergeron, Janick.
Published:	New York ,Springer, : c2006.:,
Description:	xxvi, 412 p. :ill. ; : 24 cm.;
Notes:	This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.
Subject:	Computer hardware description languages. -
Online resource:	http://www.loc.gov/catdir/enhancements/fy0663/2005938214-d.html
Online resource:	http://www.loc.gov/catdir/enhancements/fy0814/2005938214-t.html
ISBN:	0387292217 (cloth) :

Writing testbenches using System Verilog /
Bergeron, Janick.

Writing testbenches using System Verilog /by Janick Bergeron. - New York ,Springer,c2006.: - xxvi, 412 p. :ill. ;24 cm.

This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.

Includes bibliographical references and index.

ISBN: 0387292217 (cloth) :NT1500

LCCN: 2005938214Subjects--Topical Terms:

598451
Computer hardware description languages.

LC Class. No.: TK7885.7 / .B48 2006

Dewey Class. No.: 621.39/2

Writing testbenches using System Verilog /
LDR:01243cam a2200289 a 4500 001 649444
005 20100906101923.0
008 101004s2006 nyua b 001 0 eng d
010 $a 2005938214
020 $a 0387292217 (cloth) : $c NT1500
020 $a 9780387292212 (cloth)
020 $a 0387312757 (ebk.)
020 $a 9780387312750 (ebk.)
035 $a (CStRLIN)PASGA3145095-B
035 $a (PSt) (Sirsi) a3145095
035 $a 2005938214
040 $a OHX $c OHX $d NIC $d DLC $d NFU
041 0 # $a eng
042 $a lccopycat
050 0 0 $a TK7885.7 $b .B48 2006
082 0 0 $a 621.39/2 $2 22
100 1 $a Bergeron, Janick. $3 719319
245 1 0 $a Writing testbenches using System Verilog / $c by Janick Bergeron.
260 # $a New York , $c c2006.: $b Springer,
300 $a xxvi, 412 p. : $b ill. ; $c 24 cm.
500 $a This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.
504 $a Includes bibliographical references and index.
650 # 0 $a Computer hardware description languages. $3 598451
650 # 0 $a Integrated circuits $x Verification. $3 639622
700 1 # $a Bergeron, Janick. $3 719319
856 4 2 $3 Publisher description $u http://www.loc.gov/catdir/enhancements/fy0663/2005938214-d.html
856 4 1 $3 Table of contents only $u http://www.loc.gov/catdir/enhancements/fy0814/2005938214-t.html

based on 0 review(s)

Items

1 records • Pages 1 •
1

Inventory Number

No. of reservations

E033948

圖書館3F 書庫

一般圖書(BOOK)

一般圖書

621.392 B496 2006

一般使用(Normal)

On shelf

0

1 records • Pages 1 •
1

Multimedia

Reviews

Add a review and share your thoughts with other readers

Export

pickup library

Change password

Login