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Design through Verilog HDL

Tripura Sundari, B. Bala.

Design through Verilog HDL

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Design through Verilog HDL/ T.R. Padmanabhan, B. Bala Tripura Sundari.
Author:	Patma�n�apa�n, �Ti. �Ar.
other author:	Tripura Sundari, B. Bala.
Published:	Piscataway, NJ :IEEE Press ; : c2004.,
Description:	1 online resource (xii, 455 p.) :ill. :
Subject:	Verilog (Computer hardware description language) -
Online resource:	http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5236707
ISBN:	0471441481 (cloth)

Design through Verilog HDL
Patma�n�apa�n, �Ti. �Ar.

Design through Verilog HDL[electronic resource] /T.R. Padmanabhan, B. Bala Tripura Sundari. - Piscataway, NJ :IEEE Press ;c2004. - 1 online resource (xii, 455 p.) :ill.

Includes bibliographical references (p. 449-450) and index.

Machine generated contents note: 1. Introduction to VLSI Design -- 2. Introduction to Verilog -- 3. Language Constructs and Conventions in Verilog -- 4. Gate Level Modeling -- 1 -- 5. Gate Level Modeling -- 2 -- 6. Modeling at Data Flow Level -- 7. Behavioral Modeling -- 1 -- 8. Behavioral Modeling II -- 9. Functions, Tasks, and User-Defined Primitives -- 10. Switch Level Modeling -- 11. System Tasks, Functions, and Compiler Directives -- 12. Queues, Plas, and FSMS -- App. A Keywords and Their Significance -- App. B Truth Tables of Gates an Switches.

Access restricted to users at subscribing institutions of Wiley Interscience.

Mode of access: World Wide Web.

ISBN: 0471441481 (cloth)

Standard No.: 10.1002/0471723002doiSubjects--Topical Terms:

563915
Verilog (Computer hardware description language)
Subjects--Index Terms:

Electrical and Electronics Engineering.Index Terms--Genre/Form:

554714
Electronic books.

LC Class. No.: TK7885.7 / .P37 2004

Dewey Class. No.: 621.39/2

Design through Verilog HDL
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245 1 0 $a Design through Verilog HDL $h [electronic resource] / $c T.R. Padmanabhan, B. Bala Tripura Sundari.
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300 $a 1 online resource (xii, 455 p.) : $b ill.
504 $a Includes bibliographical references (p. 449-450) and index.
505 0 $a Machine generated contents note: 1. Introduction to VLSI Design -- 2. Introduction to Verilog -- 3. Language Constructs and Conventions in Verilog -- 4. Gate Level Modeling -- 1 -- 5. Gate Level Modeling -- 2 -- 6. Modeling at Data Flow Level -- 7. Behavioral Modeling -- 1 -- 8. Behavioral Modeling II -- 9. Functions, Tasks, and User-Defined Primitives -- 10. Switch Level Modeling -- 11. System Tasks, Functions, and Compiler Directives -- 12. Queues, Plas, and FSMS -- App. A Keywords and Their Significance -- App. B Truth Tables of Gates an Switches.
506 $a Access restricted to users at subscribing institutions of Wiley Interscience.
538 $a Mode of access: World Wide Web.
650 0 $a Verilog (Computer hardware description language) $3 563915
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653 $a Electrical and Electronics Engineering.
655 4 $a Electronic books. $2 local $3 554714
700 1 $a Tripura Sundari, B. Bala. $3 771685
710 2 $a John Wiley & Sons. $3 771620
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