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Design and test technology for depen...

Ubar, Raimund, (1941-)

Design and test technology for dependable systems-on-chip

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Design and test technology for dependable systems-on-chip/ Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
其他作者:	Ubar, Raimund,
出版者:	Hershey, Pa. :IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), : c2011.,
面頁冊數:	xxv, 550 p. :ill. ; : 29 cm.;
標題:	Systems on a chip - Design and construction. -
電子資源:	http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/978-1-60960-212-3
ISBN:	9781609602147 (ebook)

Design and test technology for dependable systems-on-chip
Design and test technology for dependable systems-on-chip[electronic resource] /Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors. - Hershey, Pa. :IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA),c2011. - xxv, 550 p. :ill. ;29 cm.

Includes bibliographical references.

Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).

Mode of access: World Wide Web.

ISBN: 9781609602147 (ebook)Subjects--Topical Terms:

636566
Systems on a chip
--Design and construction.Subjects--Index Terms:

Built-in self repair for logic structures

LC Class. No.: TK7895.E42 / D467 2011e

Dewey Class. No.: 621.3815

Design and test technology for dependable systems-on-chip
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245 0 0 $a Design and test technology for dependable systems-on-chip $h [electronic resource] / $c Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
260 $a Hershey, Pa. : $b IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), $c c2011.
300 $a xxv, 550 p. : $b ill. ; $c 29 cm.
504 $a Includes bibliographical references.
520 3 $a Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).
538 $a Mode of access: World Wide Web.
650 0 $a Systems on a chip $x Design and construction. $3 636566
650 0 $a Networks on a chip $x Design and construction. $3 805450
650 0 $a Systems on a chip $x Testing. $3 655639
650 0 $a Networks on a chip $x Testing. $3 805451
653 $a Built-in self repair for logic structures
653 $a Combined test-data compression and test planning
653 $a Diagnostic modeling of digital systems
653 $a Fault simulation and fault injection technology
653 $a Fault-tolerant and fail-safe design based on reconfiguration
653 $a Flexible fault-tolerant schedules for embedded systems
653 $a Memory testing and self-repair
653 $a Optimizing fault tolerance for multi-processor system-on-chip
653 $a Software-based self-test of embedded microprocessors
653 $a Transient faults detection and compensation
700 1 $a Ubar, Raimund, $d 1941- $3 805447
700 1 $a Raik, Jaan, $d 1972- $3 805448
700 1 $a Vierhaus, Heinrich Theodor, $d 1951- $3 805449
710 2 $a IGI Global. $3 805187
856 4 1 $3 Chapter PDFs via platform: $u http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/978-1-60960-212-3

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