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Design and test technology for depen...
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Ubar, Raimund, (1941-)
Design and test technology for dependable systems-on-chip
Record Type:
Language materials, printed : Monograph/item
Title/Author:
Design and test technology for dependable systems-on-chip/ Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
other author:
Ubar, Raimund,
Published:
Hershey, Pa. :IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), : c2011.,
Description:
xxv, 550 p. :ill. ; : 29 cm.;
Subject:
Systems on a chip - Design and construction. -
Online resource:
http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/978-1-60960-212-3
ISBN:
9781609602147 (ebook)
Design and test technology for dependable systems-on-chip
Design and test technology for dependable systems-on-chip
[electronic resource] /Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors. - Hershey, Pa. :IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA),c2011. - xxv, 550 p. :ill. ;29 cm.
Includes bibliographical references.
Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).
Mode of access: World Wide Web.
ISBN: 9781609602147 (ebook)Subjects--Topical Terms:
636566
Systems on a chip
--Design and construction.Subjects--Index Terms:
Built-in self repair for logic structures
LC Class. No.: TK7895.E42 / D467 2011e
Dewey Class. No.: 621.3815
Design and test technology for dependable systems-on-chip
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Design and test technology for dependable systems-on-chip
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Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
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Hershey, Pa. :
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IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA),
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c2011.
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xxv, 550 p. :
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ill. ;
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29 cm.
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Includes bibliographical references.
520
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Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).
538
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Mode of access: World Wide Web.
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Systems on a chip
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Design and construction.
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636566
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Networks on a chip
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Design and construction.
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Systems on a chip
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Testing.
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655639
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Networks on a chip
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Testing.
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Built-in self repair for logic structures
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Combined test-data compression and test planning
653
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Diagnostic modeling of digital systems
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Fault simulation and fault injection technology
653
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Fault-tolerant and fail-safe design based on reconfiguration
653
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Flexible fault-tolerant schedules for embedded systems
653
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Memory testing and self-repair
653
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Optimizing fault tolerance for multi-processor system-on-chip
653
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Software-based self-test of embedded microprocessors
653
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Transient faults detection and compensation
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Ubar, Raimund,
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1941-
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805447
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Raik, Jaan,
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1972-
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805448
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Vierhaus, Heinrich Theodor,
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1951-
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805449
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IGI Global.
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Chapter PDFs via platform:
$u
http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/978-1-60960-212-3
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